I don't know where one might submit a bug report for the Intel FPGA IP so I submit one here.
When I configure the Intel/Altera CIC Digital Filter IP for Hogenauer pruning I noticed that the single lowest signed two's complement fixed point value produces a non-deterministic result. When I change the output-rounding option to truncation this problem vanishes.
Here is my CIC configuration.
14 input bits.
22 output bits (yes, probably optimistic).
1 differential delay
16 decimation rate change factor
1 channel per interface
Hogenauer-pruning, output rounding option
I tried narrowing my CIC output to 18 bits from 22 bits, but it does not fix (the problem that the single lowest signed two's complement input causes an anomalous output when Hogenauer pruning is enables in the CIC IP's output rounding option). Possibly, Intel's lookup table for the CIC IP internal number of CIC accumulator bits, is defective.
Maybe we have no choice other than to turn off Hogenauer pruning output rounding option, and use instead now the other low resource consuming option which is truncation.
Ok, so the obvious solution is to artificially add one more bit to the CIC input, sign extending the two's complement fixed point by one bit, and then Hogenauer pruning CIC output rounding option can be turned back on, and the anomalous/erroneous/non-determanistic CIC output value occurring in a DC linearity test for the single most negative fixed point input value is eliminated.
Sorry for the delay. This case was just routed to me. As I read through the discussion, seems like you have managed to resolve the initial problem.
Just would like to check with you if there is any other specific problem that I can further assist.
Please let me know if there is any concern. Thank you.
Thanks for your sharing. I would like to bring this to our Factory for them to look into future enhancement in IP or to the documentation. Would you mind to share with me some Modelsim simulation test case which replicate the problem observation and also the passing test case after adding your workaround. This would be helpful for the Factory to have further insight into this. Thank you very much for your help.
Would you mind to share with me some Modelsim simulation test case which replicate the problem observation and also the passing test case after adding your workaround.
No doubt that providing such input would speed resolution, but also this requires some effort on my part, and since I have a workaround and also a long list of other higher priority tasks that I need to accomplish, its unlikely for unfunded tasks to float to the top of my list.
Thanks for your update. I understand your concern and priorities. I would feedback the current available information to Engineering for them to look into. Thank you very much for your help.
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