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AN 729: JESD204B IP Reference Design


I am currently trying out this example with a slight modification required for my hardware setup. I am using an Arria 10 10AS027H4F34I3SG DEVICE. I have both a USB Blaster II and an Ethernet Blaster but I can't debug the example as per the guide in the AN 729 document.


That example uses a NIOS II as a control unit. I have also tried the generic examples that can be generated in Platform Designer for the JESD204B IP. I have tried both, the NIOS II and RTL versions.


With the NIOS II versions, I can't download my code using the Nios II Software Build Tools for Eclipse. I always get the error "Downloading ELF Process failed". The example compiles fine with no errors.


With the RTL version, after successfully compiling and programming the device, the system console tool cannot connect to the device either despite the device being detected properly by the tool.


I was wondering I need a paid license to use the JESD204B examples. I know I cannot generate programming files but how can I evaluate the examples without debugging capabilities?



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2 Replies

Hi Michael,

The free Intel® FPGA IP Evaluation Mode allows you to evaluate the licensed Intel® FPGA IP cores in simulation and hardware before purchase. You can generate time limited programming files (<project name>_time_limited.sof) that expires at the time limit.

Please refer this JESD204B Intel® FPGA IP Evaluation Mode User Guide

All the Best !!

Kshitij Goel

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Hi Michael,

We do not receive any response from you to the previous reply that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

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