ATX PLL in the DisplayPort IP generated design example

[Rk_Athram]

Hi,

I have gone through the UG :Intel® Arria® 10 DisplayPort IP Core Design Example User Guide
UG-20075, and example design

https://fpgacloud.intel.com/devstore/platform/17.0.0/Standard/arria-10-displayport-4kp60-with-video-and-image-processing-pipeline-re-transmit-reference-design/

In this it uses FPLL and stores calibrated link rates for different speeds. and while changing from one speed to other calibration is not required.

My query is

1)can use ATX PLL instead of FPLL ?

2)Does ATX Pll supports storing link rate feature ? without using Multiple Reconfiguration Profiles!

Regards,

Rajesh

[Rk_Athram]

In display port design for FPLL is used, which having registers to store the frequency band, the similar registers are not available for ATX PLL. 

SNAPSHOT FROM A10 register map excel sheet.

I need to figure out whether i can use the existing logic from display port for switching speed when i use ATX PLL without re calibrating after changing speed?

[Rk_Athram]

Hi,

These registers are available in FPLL section, and these are used for storing link rate and load back the link rate,

can these registers will work for ATX PLL too ?