I face one problem, now I need use lvds serdes to do one transmitter, I need to get one dedicated clk for IO_PLL (I need external pll mode) from another bank due to the pin assignment for data lane and clock lane assignment at current bank. So I run the I/O assignment analysis in the pin planner, there is always one LVDS_CLK_TREE error, which means that this solution can not complete.
About above the problem, I found that the lvds serdes ip can droven by the IO_PLL from its adjacent bank, so I do not know what happens, could someone give me some advice?
FPGA : 10ax115n2f45e1sg
quartus pro : 16.0
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