Can we check on few things:
1. Is your external clock source cleaned? Before reconfiguration happened, is the PLL able to lock and produce correct output clock frequency?
2. What is the expected output and what is the output you obtained after reconfiguration?
3. Are you able to share your sample design together with the testbench?
Hi Eng Wei,
For the question you care:
1. external clock source is clean and pll can lock before reconfiguration;
2. I want to get 12Mhz output, but the output is close to the 24Mhz ( it's almost the same with the output frequency before reconfiguration).
3. Because of comfidentiality principle, I have no power to share the code, sorry.
Could you build one case, and see that you will get the same result?
there might be some issue with older version of Quartus:
Are you able to move to newer version of Quartus? Also, can you check if you have post scale counter being cascaded? Cascading post scale counter will not work for reconfiguration.