About timing of signal BUSY in Altera ASMI Parallel IP Core

[pwiln]

​In user guide of ASMI Parallel IP core (document UG-ALT1005  2018.05.15)

In figure 9  : Fast Reading Multiple-Byte

signal Busy goes to '1' on rising edge of clkin and back to '0' on falling edge of clkin  .

generally the same phase of the  clock cause change on signal ?

In figure 19 : command  4BYTEADDREN

signal Busy goes to '1' on rising edge of clkin and back to '0' on rising edge of clkin  .

 I need to know on which phase of clkin  signal busy change in order to know which phase of clkin to use in my logic  for sampling the signal busy ?

[ShafiqY_Intel]

Hi,

You can use both of these condition.

However, my strongly recommendation for sampling the busy signal is Busy signal goes to '1' on rising edge of clkin and Busy signal goes to '0' on falling edge of clkin.

In addition, when the busy signal goes to ‘0’, please allow two clock cycles before sending a new signal.

Thanks.😉 😉