FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6404 Discussions

Accessing rx_frm_type[3:0] signals from TSE

Honored Contributor II

TSE IP. accessing rx_frm_type[3:0] signals (Avalon ST receive interface) from verilog? 


All the documentation indicates the signals are there (full TSE w/FIFO's) and although not acessible in QSYS they exist. However try as I might I cannot seem to get my verilog monitor.v component to connect to these signals. 


In my application, I must monitor and act on Frame types in realtime. I.e. VLAN frame decoding, broadcast/multicast filtering, etc. 


I can't see what I am missing. :confused: 


Please help!
0 Kudos
0 Replies