Agilex 7 LVDS SERDES IP : Wrong behavior in simulation (coreclock too slow)

[jaime_e-space]

Hello,

I've been trying to simulate the LVDS SERDES IP (6-bit) on my design with Questa Intel FE, and it looks like there is something weird with the coreclock output (both in TX and RX).  I see the same problem either in internal or external PLL modes. In addition, I have generated the Example Design, and the problem persists (of course, the testbench checker fails).

The issue is that the coreclock is about 30 times slower than expected.

Here you can find some screenshots:

1) Initially, the ext_lvds_clk is a slow clock. In this case, ext_loaden is triggered every 6 cycles, and tx_coreclock is coherent too. 

But then the ext_lvds_clk switches to the fast clock, and we can see that ext_loaden remains coherent to that clock, but tx_coreclock doesn't.

2) Looking more in detail, we can see that coreclock remains low for 3 cycles (that's correct), but it remains high for many more cycles than 3. In consequence, most of the input samples are skipped.

3) The same situation persists once the SERDES IP locks. As a result, the same input word is serialized several times over and over again for each coreclock cycle.

For information, I'm using Quartus Prime Edition 24.3

Is there anything I'm doing wrong?

Thanks in advance!

Jaime

[Farabi]

Hello Jaimie,

I am taking over this case from previous owner.

From the information you provided, the coreclk remains high for much longer than expected. This caused input samples to be skipped, resulting in repeated serialization of the same input word.

Can you observed the PLL is locked all the time during the transition?

regards,

Farabi

[jaime_e-space]

Hello Farabi,

At the end I found the solution. The simulation doesn't accept to start with an asserted reset. Instead, if I toggle the reset, the right behavior is found...

Regards

Jaime