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Hi,
i've got a question! How do you work with the altera FIFO megafunction? I don't know how to handle the FIFO, because the status signals are updated one or two clock cycles after reading/writing... E.g.: How can I fast read data from the fifo (every clock cycle one read operation)? For example my own logic isn't able to determine some clock cycles in the futer if it is able to process new data from the FIFO. In my case I need fast read and write operations, but I only can assign one clock cycle in the futer if I continue or stop reading/writing... Do you know what I mean? How do you handle the Altera FIFO? Thanks for every hint!Link Copied
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you should only moniter the signals on the side of the FIFO you are looking at, you should never anticipate when data will be ready.
On the write side of the fifo, you can keep writing on every clock cycle until it is full (and you can set a nearly full threshold to help you control). and on the read side you can keep reading until it is empty.- Mark as New
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--- Quote Start --- you should only moniter the signals on the side of the FIFO you are looking at, you should never anticipate when data will be ready. On the write side of the fifo, you can keep writing on every clock cycle until it is full (and you can set a nearly full threshold to help you control). and on the read side you can keep reading until it is empty. --- Quote End --- Hi, To read fast and simple from the fifo( do this with underflow protection and show ahead ON): When read_state => Read<='1'; if read='1' and empty='0' then .... if (done_condition_variable='1') then read<='0'; state<=other_state: end if; end if:
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--- Quote Start --- Hi, To read fast and simple from the fifo( do this with underflow protection and show ahead ON): When read_state => Read<='1'; if read='1' and empty='0' then .... if (done_condition_variable='1') then read<='0'; state<=other_state: end if; end if: --- Quote End --- This code makes very little sense without context, and you're reply to a thread that is 6 years old!

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