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Altera Generic Tri-state Controller optimization for ZBT SRAM

Honored Contributor II

Hello, i'm using EP4CGX150DF31 on custom PCB with dual Cypress NoBL (= Zero Bus Turnaround) SSRAM CY7C1463AV33. 

Theoretical Bandwidth 32 bits x 65 MHZ (memclk speed) = 2080 Mbit/s 


QSYS SRAM ios:  

.sram_tcm_address_out 21 of 23 hight bits connected to SRAM Address bus 

.sram_tcm_byteenable_n_out all 4 bits connected to SRAM BWx pins 

.sram_tcm_read_n_out connected to SRAM OE pin 

.sram_tcm_write_n_out connected to SRAM WE pin 

.sram_tcm_data_out connected to SRAM DATA bus 

.sram_tcm_chipselect_n_out connected to CE1, CE2, CE3 according it's polaritys  


I used NIOS II EDS Standart memory test program and achieved stable work using the following Generic Tri-state controller parameters:  

(see GTC_params PNGs in attachment) 

Read wait time: 1 

Wite wait time: 0 

Setup time: 0 

Data Hold Time: 1 

Maximum pending data transactions: 64 

Turnaround time: 0 

Timing units: Cycles 

Read latency: 2 

Chipselect through read latency is checked 


But when i try to use this memory in Video proccessing (all standart Altera Cores): 

PAL Video ADC -> CVI -> frame buffer -> CVO -> PAL Video DAC  

Clocked Video Output Underflow and my ext monitor lost video synchronization very often 

PAL video uses total 54 MBit/s maximum bandwith for read and write operation. 


I try to analyze behavior of Generic Tri-State Controller with SignalTap LA and got this (stap PNGs in attachment) 

and saw that reading/writing 1 word use 3-5 clock cycles -> my bandwith is too slow 


1) Does this Altera Core support ZBT/NoBL SRAM? 

2) Have you any ideas, how to properly setup Generic Tri-State controller for this NoBL SRAM? 

3) Does Altera provide any tool for measure external SRAM efficiency/bandwith on Cyclone IV FPGA? 



P.S. Sorry for my English, it's not my native language.
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2 Replies
Honored Contributor II

Hello again. 

I've find optimum parameters for Cypress ZBT SRAM.  

Maybe it can be usefull for anyone else. 


Read wait time: 0 

Wite wait time: 0 

Setup time: 0 

Data Hold Time: 0 

Maximum pending data transactions: 64 

Turnaround time: 0 

Timing units: Cycles 

Read latency: 3 

Chipselect through read latency is unchecked 

Full preset for Generic Tri-state controller in attachment 


And else I had to instatiate PLL and shift 65 MHZ clock which drive SRAM's CLK pin to -3.07 ns. All other logic driven by not shifted clock. 



New SignalTap images of Read/Write operation: 

https://www.alteraforum.com/forum/attachment.php?attachmentid=8439 https://www.alteraforum.com/forum/attachment.php?attachmentid=8440 https://www.alteraforum.com/forum/attachment.php?attachmentid=8441  


Good luck
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Honored Contributor II

Hello KWler, 

I found your post very interesting. I have to manage a similar SRAM and I'm struggling with it with a similar QSys system. 

I would like to ask you some question: 

1) Why do you put ".sram_tcm_address_out 21 of 23 hight bits connected to SRAM Address bus" if you have only 21 bits for address? Is there a reason or you could put directly 21? 

2) Why do you use only 65 MHz if your memory could work at 133 MHz? (Silly question, but maybe you have a reason to make the SRAM working at half of its maximum speed) 

3) What is the type of memory are you using? The 1Mx36 or the 2Mx18 one? I can't understand it from your parameters, you chose Data width 32 but in the module assignments window you put SRAM_Data_width 16; 

4) Are Parameters in the "Module Assignment" window important? I don't have a CPU or a NIOS attached (it is a straight system), if I understand well they are parameters only important for software. 

5) Have you a reason to put the SRAM clock shifted? I found thin solution also in other projects and I would like to understand why.  


Thank you
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