FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.

Arria 10 DDR4


Hi! I'm working with a board based on Arria10 and DDR4 device MT40A512M16LY-062E.
Question 1. I'm trying to handle this behaviour of i_amm_request signal (Att. 1) when it is deasserted fora long time. Can it be a periodic OCT calibration? I have turned it off in IP parameter editor, but nothing changes. 

Question 2. In IP parameter editor when I'm trying to enable Memory-Mapped Configuration and Status Register (MMR) Interface (want to get access to internal registers), I receive an error (Error: emifddr4.emif_0.ctrl_mmr_slave_0: Interface must have an associated clock) and two messages:  - Warning: emifddr4.emif_0: You have exported the interface ecc_core.ctrl_mmr_slave_0 but not its associated clock interface. Export the driver of ecc_core.emif_usr_clk;
Warning: emifddr4: You have exported the interface emif_0.ctrl_mmr_slave_0 but not its associated clock interface. Export the driver of associatedClock of emif_0.ctrl_mmr_slave_0.

0 Kudos
1 Reply

Attachment 1