Arria 10 External Memory Interface Invalid Data Width

[Altera_Forum]

I am using the External Memory Interface IP core in Qsys to connect to a DDR3 daughter memory card through the Arria 10 GX FPGA Development Kit via the HiLo interface. I am also using an address span extender between the CPU and EMI the connects to the EMI's ctrl_amm_0 port; there is an error claming that the data width of this connection must be of power of two and between 8 and 4096. I'm not sure how to check the current data width or what I need to change to get the size to a power of two.

[Altera_Forum]

--- Quote Start ---  I am using the External Memory Interface IP core in Qsys to connect to a DDR3 daughter memory card through the Arria 10 GX FPGA Development Kit via the HiLo interface. I am also using an address span extender between the CPU and EMI the connects to the EMI's ctrl_amm_0 port; there is an error claming that the data width of this connection must be of power of two and between 8 and 4096. I'm not sure how to check the current data width or what I need to change to get the size to a power of two.  --- Quote End ---    I had the same issue in Qsys and resolved it by regenerating the EMIF core wtih a DQ width of 64 (8 pins per DQS group) instead of the 72 that is supported on my board. I was able to generate the core outside of Qsys using the IP Parameter Editor though without any problems.

[Jacky_chang]

hji

about

"regenerating the EMIF core wtih a DQ width of 64 (8 pins per DQS group)"

Is there a picture of the regenerating process?

I have the same problem

address width above 32 bits are not supported in nios 2

[Altera_Forum]

--- Quote Start ---  I am using the External Memory Interface IP core in Qsys to connect to a DDR3 daughter memory card through the Arria 10 GX FPGA Development Kit via the HiLo interface. I am also using an address span extender between the CPU and EMI the connects to the EMI's ctrl_amm_0 port; there is an error claming that the data width of this connection must be of power of two and between 8 and 4096. I'm not sure how to check the current data width or what I need to change to get the size to a power of two.  --- Quote End ---    Hi, certain EMIF IP presets include ECC thus the DQ width is not the power of two (for example, instead of x64 you will get x72). If you are using Nios II as the CPU, you can navigate to the "Advanced Features" and tick "ECC Present" (I am using Quartus 16.0, name could be different in other versions). Doing so will create a Avalon Streaming Source for ECC event (which you can connect to a AVST sink) - and at the same time allow the EMIF with ECC enabled to connect to Nios

[Altera_Forum]

--- Quote Start ---   There is an error claming that the data width of this connection must be of power of two and between 8 and 4096. I'm not sure how to check the current data width or what I need to change to get the size to a power of two.  --- Quote End ---    Hello,   Please have a look at attached image. If you enable error detection and correction logic with ecc option under controller tab, this error should vanish.  Sorry for responding to old thread. But thought it could be useful to someone as we also faced same issue here.  Cheers, Bhaumik