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Hi,
We are trying to use the Transceiver Toolkit to verify a JESD204b link to work out the best receiver parameters for our link.
Unfortunately the ADC we are using is not capable of outputting a raw PRBS pattern. The only patterns it can generate are made prior to the 8/10b encoder. As a result the hard PRBS checkers on the Arria 10 are not usable because they perform checking before the 8/10b decoder.
I am trying to determine if it is possible to use the Avalon-ST Data Pattern Checker core connected up to the PCS data output (i.e. after the 8/10b decoder) in conjunction with the Transceiver Toolkit to allow the automatic sweep tests to be performed.
Could you provide instructions whether it is possible to connect up the Avalon-ST Data Pattern Checker (or some other custom soft PRBS checker) to the ADME endpoint in the Native Transceiver core?
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Hi,
User custom pattern can be sent through the tx_parallel_data port only. The NPDME adds the JTAG master interface only so that user can easily connect to internal register space via system console.
Regards
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I could be misunderstanding something, but I'm not sure how that helps me.
I don't have any of the transmitter lanes broken out on the board, and simply looping back within the transceiver lane in the FPGA surely doesn't help me test the BER of an incoming receive lane.
Or are you saying that the transceiver can directly compare the incoming data on the RX lane from outside the FPGA with that of the transmit lane (as it it were a loopback external to the FPGA)?
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Hi,
Sorry I may have misunderstood your query earlier.
For your case, I think the following training, specifically section 4 of the training will help you understand how to use a soft pattern generator and checker with the transceiver toolkit.
Regards

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