I'm a bit confused on the several template variations, pipeline/burst etc.
For example, I see there's different templates for reading and writing, yet for the nios to execute from it (including placing the stack/heap in it), it has to do both. So, in order to connect the nios' instruction/data to it in qys, , I'm imagining a single component would have to be created/instantiated that has both pipwline read and simple write templates.. is this correct?
Or Is there perhaps a better way of doing this? Not to complicate matters, but the "external memory", is actually a fifo (implemented in logic), that's closely tied to an sdram ip... if that helps!
Thanks!
