Avalon MM clock crossing bridge not passing signals from slave intf to master intf

[Altera_Forum]

Hi 

 I am using Qsys 15.0. I am working on a hierarchical Qsys project, integrating altera's V series PCIe3 IP into my system. All the pcie stuff is within a qsys subsytem called 'pcie_subsystem'.  pcie_subsystem is instantiated inside a module in a verilog file. Then this module is created as a component in itself, lets call this component 'interfaces_subsystem'. I wrote the *_hw.tcl for this.  Finally in my application I create an instance of interfaces_subsystem component and hook it up with my custom logic.  I want to expose the BAR and TXS interfaces from the pcie ip to my application running at a different clock frequency. Hence I decided to use the Avalon MM clock crossing bridge.  The problem is that when I send a read/write command via the BAR, the bridge doesnt forward it to the next interfaces_subsystem. I checked my design in logic analyzer and I saw that the read/write generated by the BAR interface propagates all the way to the s0 interface of my mm_clock_crossing_bridge_bar but the m0 interface doesn't reproduce a similar transaction.  I have attached a snapshot of my qsys pcie_subsystem with bridges. Below is the code snippet from my *_hw.tcl of interfaces_subsystem. I am not sure if I should include the bridgeToMaster property and if I should I dont know how. Because one side of the bridge is in another subsytem.  # # connection point pcie3_bar2_avalon_mm_master# add_interface pcie3_bar2_avalon_mm_master avalon master# set_interface_property pcie3_bar2_avalon_mm_master addressAlignment NATIVE set_interface_property pcie3_bar2_avalon_mm_master addressUnits SYMBOLS set_interface_property pcie3_bar2_avalon_mm_master associatedClock "****_clk" set_interface_property pcie3_bar2_avalon_mm_master associatedReset "application_reset_n" set_interface_property pcie3_bar2_avalon_mm_master bitsPerSymbol 8 set_interface_property pcie3_bar2_avalon_mm_master burstOnBurstBoundariesOnly false set_interface_property pcie3_bar2_avalon_mm_master burstcountUnits WORDS# set_interface_property pcie3_bar2_avalon_mm_master explicitAddressSpan 0 set_interface_property pcie3_bar2_avalon_mm_master holdTime 0 set_interface_property pcie3_bar2_avalon_mm_master linewrapBursts false set_interface_property pcie3_bar2_avalon_mm_master maximumPendingReadTransactions 1 set_interface_property pcie3_bar2_avalon_mm_master readLatency 0 set_interface_property pcie3_bar2_avalon_mm_master readWaitTime 1 set_interface_property pcie3_bar2_avalon_mm_master setupTime 0 set_interface_property pcie3_bar2_avalon_mm_master timingUnits Cycles set_interface_property pcie3_bar2_avalon_mm_master writeWaitTime 0 set_interface_property pcie3_bar2_avalon_mm_master ENABLED true set_interface_property pcie3_bar2_avalon_mm_master EXPORT_OF "" set_interface_property pcie3_bar2_avalon_mm_master PORT_NAME_MAP "" set_interface_property pcie3_bar2_avalon_mm_master SVD_ADDRESS_GROUP "" add_interface_port pcie3_bar2_avalon_mm_master pcie_bar2_waitrequest waitrequest Input 1 add_interface_port pcie3_bar2_avalon_mm_master pcie_bar2_readdata readdata Input 256 add_interface_port pcie3_bar2_avalon_mm_master pcie_bar2_readdatavalid readdatavalid Input 1 add_interface_port pcie3_bar2_avalon_mm_master pcie_bar2_burstcount burstcount Output 1 add_interface_port pcie3_bar2_avalon_mm_master pcie_bar2_writedata writedata Output 256 add_interface_port pcie3_bar2_avalon_mm_master pcie_bar2_address address Output 20 add_interface_port pcie3_bar2_avalon_mm_master pcie_bar2_write write Output 1 add_interface_port pcie3_bar2_avalon_mm_master pcie_bar2_read read Output 1 add_interface_port pcie3_bar2_avalon_mm_master pcie_bar2_byteenable byteenable Output 32 add_interface_port pcie3_bar2_avalon_mm_master pcie_bar2_debugaccess debugaccess Output 1 set_interface_assignment pcie3_bar2_avalon_mm_master embeddedsw.configuration.isFlash 0 set_interface_assignment pcie3_bar2_avalon_mm_master embeddedsw.configuration.isMemoryDevice 0 set_interface_assignment pcie3_bar2_avalon_mm_master embeddedsw.configuration.isNonVolatileStorage 0 set_interface_assignment pcie3_bar2_avalon_mm_master embeddedsw.configuration.isPrintableDevice 0 # # connection point pcie3_txs_avalon_mm_slave# add_interface pcie3_txs_avalon_mm_slave avalon slave# set_interface_property pcie3_bar2_avalon_mm_master addressAlignment NATIVE set_interface_property pcie3_txs_avalon_mm_slave addressUnits SYMBOLS set_interface_property pcie3_txs_avalon_mm_slave associatedClock "****_clk" set_interface_property pcie3_txs_avalon_mm_slave associatedReset "application_reset_n" set_interface_property pcie3_txs_avalon_mm_slave bitsPerSymbol 8 set_interface_property pcie3_txs_avalon_mm_slave burstOnBurstBoundariesOnly false set_interface_property pcie3_txs_avalon_mm_slave burstcountUnits WORDS# set_interface_property pcie3_bar2_avalon_mm_master explicitAddressSpan 0 set_interface_property pcie3_txs_avalon_mm_slave holdTime 0 set_interface_property pcie3_txs_avalon_mm_slave linewrapBursts false set_interface_property pcie3_txs_avalon_mm_slave maximumPendingReadTransactions 8 set_interface_property pcie3_txs_avalon_mm_slave readLatency 0 set_interface_property pcie3_txs_avalon_mm_slave readWaitTime 0 set_interface_property pcie3_txs_avalon_mm_slave setupTime 0 set_interface_property pcie3_txs_avalon_mm_slave timingUnits Cycles set_interface_property pcie3_txs_avalon_mm_slave writeWaitTime 0 set_interface_property pcie3_txs_avalon_mm_slave ENABLED true set_interface_property pcie3_txs_avalon_mm_slave EXPORT_OF "" set_interface_property pcie3_txs_avalon_mm_slave PORT_NAME_MAP "" set_interface_property pcie3_txs_avalon_mm_slave SVD_ADDRESS_GROUP "" add_interface_port pcie3_txs_avalon_mm_slave pcie_txs_waitrequest waitrequest Output 1 add_interface_port pcie3_txs_avalon_mm_slave pcie_txs_readdata readdata Output 32 add_interface_port pcie3_txs_avalon_mm_slave pcie_txs_readdatavalid readdatavalid Output 1 add_interface_port pcie3_txs_avalon_mm_slave pcie_txs_burstcount burstcount Input 1 add_interface_port pcie3_txs_avalon_mm_slave pcie_txs_writedata writedata Input 32 add_interface_port pcie3_txs_avalon_mm_slave pcie_txs_address address Input 64 add_interface_port pcie3_txs_avalon_mm_slave pcie_txs_write write Input 1 add_interface_port pcie3_txs_avalon_mm_slave pcie_txs_read read Input 1 add_interface_port pcie3_txs_avalon_mm_slave pcie_txs_byteenable byteenable Input 4 add_interface_port pcie3_txs_avalon_mm_slave pcie_txs_debugaccess debugaccess Input 1 set_interface_assignment pcie3_txs_avalon_mm_slave embeddedsw.configuration.isFlash 0 set_interface_assignment pcie3_txs_avalon_mm_slave embeddedsw.configuration.isMemoryDevice 0 set_interface_assignment pcie3_txs_avalon_mm_slave embeddedsw.configuration.isNonVolatileStorage 0 set_interface_assignment pcie3_txs_avalon_mm_slave embeddedsw.configuration.isPrintableDevice 0