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Altera_Forum
Honored Contributor I
734 Views

Avalon-ST vs Descriptor/Data in pcie ip 9.1

In the PCI Express Megafunction, two options are provided for the interface between ip core and application: 

Descriptor/Data and Avalon-ST, and the latter is recommended by Altera in the User's Guide. 

 

However, as I read through the VHDL code of the chaining dma example using Avalon-ST, I found that, we first interface with ip core using A-ST, and then we use a module to change the A-ST to Descriptor/Data. The datapath is : 

core --> core to A-ST --> A-ST to D/D --> App 

 

And if we use D/D instead, the datapath is: 

core --> core to D/D --> App 

 

From the app layer's perspective, both options provides the same interface. So why not use D/D directly and bother to use A-ST ? Is there any advantage we can make from the Avalon-ST?
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3 Replies
Altera_Forum
Honored Contributor I
39 Views

still no reply..

Altera_Forum
Honored Contributor I
39 Views

I kind of wondered the same thing. I know there was honestly a good reason i thought as to why i chose the avalone interface with the D/D adapter, but that was a few years ago for me and can't quite remember. I have been anxious to see if anyone else knew.

Altera_Forum
Honored Contributor I
39 Views

It sounds like it was the fastest way to re-use the existing Desc/Data chaining DMA design.

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