Avalon Streaming Interface VHDL templates

[Altera_Forum]

Has anyone got any Avalon Streaming Interface VHDL templates? 

 I want to interface an A/D to an FIR to an avalon memory interface.  thanks

[Altera_Forum]

I'm not sure that there are any, but it's easy to implement... Just put your data on the data bits, assert 'valid' when the data from the A/D is there, and wait until 'ready' is asserted. When it is, de-assert 'valid' and prepare the next data word.

[Altera_Forum]

to read from a dual channel FIR, multi-cycle (7 clocks) is the following correct, 

 ch1: ast_SOP=1 AND ast_VALID=1  ch2 ast_EOP=1 AND ast_VALID=1  VALID will only be high for one clock cycle

[Altera_Forum]

It is very difficult to answer you on two different threads. Just pick one. 

 Valid should be high for one cycle only if Ready is asserted. If not you must wait until it is.