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Altera_Forum
Honored Contributor I
720 Views

Avalon Timing for onchip memory

Hey All, 

I'm working off the Cyclone V GT dev kit, and trying to modify the PCIe dma example design that uses on chip dual port ram. I'm writing a module that will interface with an external source and act as an Avalon master to write to the dual port ram. The trouble I'm having is I can't find a timing diagram for the avalon slave interface of the On-Chip Memory (altera_avalon_onchip_memory2 in Qsys.) Specifically, the slave interface does not include a waitrequest signal or any of the burst write signals. The latency can be set with the Qsys editor to 1 or 2, but I'm not sure that is enough detail to implement the master side of the interface. I suppose the clock enable could be used as an on/off switch between writes, but I'm hoping there is a faster option, similar to burst writing. 

 

I imagine this info or timing diagram is available somewhere, but I'm unable to locate it.  

 

So the boiled down version of the question is: What is the Avalon memory mapped timing for the on chip memory? 

 

Thanks
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Altera_Forum
Honored Contributor I
25 Views

Qsys should take care of all the master-slave interfacing - the whole point of using Qsys is that you do not need to worry about the IP to Avalon timing. 

Just to answer your question though, the onchip RAM doesn't have waitstates, so in exclusive use (single master connection) the waitrequest signal seen at the master is always disabled. Also because onchip RAM is a parallel bus, where the address/data is available on a single clock cycle with zero waitstates for both read/write, burst mode does not exist for such slave. 

Again, Qsys is able to adapt your master (as long it is an AvalonMM type) to the slave interface, and create additional pipelining/waitstates to match.
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