Hi! I'm using the automatically generated PCIe reference design (chaining DMA) with the root port bus functional model (BFM).
I got some questions regarding incoming transactions handling: 1) What file/module/task handles incoming PCIe write requests, that are sent by the endpoint (the one I put instead of chaining DMA)? All I can see is BFM silently putting all the needed data from a write request it received into the shared memory. But what I need to do is to decode this incoming TLP with a write request myself and send it one level higher (I have my own wrapper for the pciex_mgwz_chaining_testbench that wants to get data sent via PCIe, not to have it written into the shared memory). 2) What part of the design handles read requests? I need to do the same thing: intercept all read requests at the BFM side sent by my endpoint and send them one level higher so that driver that lives there could handle these read requests. 3) Is it possible to send the completion manually from the testbech? I know I can send a write request to the endpoint (I use ebfm_barwr_imm procedure), but how to assemble a completion request by myself?