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Altera_Forum
Honored Contributor I
993 Views

BRAM "Read old data while writing" option for Cyclone V

Hi,  

I am using Cyclone V device and I wanted to migrate one of the design which was targeted for xilinx device to Altera Cyclone V. And I want to use True Dual Port BRAM with "Read Old data while writing" feature. But when I tried to generate the BRAM IP using MegaWizard Plug-In manager, there is no option to tell "Read old data while writing" mode. When I checked in the Altera 'Embedded memory User guide' document, found that this feature is not supported for M10K and M20K blocks. So is it possible to use True Dual port BRAM with "Read Old data during write" feature, in Cyclone V? If not what is the alternate solution? 

 

Thanks in advance..
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6 Replies
Altera_Forum
Honored Contributor I
36 Views

As I read in Embedded memory user guide, "Read old data during write" is not supported in M10K and M20K blocks. Since Cyclone V device has only M10K blocks, can I assume that "Read old data during write" is not possible in Cyclone V? If yes, what is the alternate solution for this? Looking forward for help.. Thanks.

Altera_Forum
Honored Contributor I
36 Views

 

--- Quote Start ---  

As I read in Embedded memory user guide, "Read old data during write" is not supported in M10K and M20K blocks. Since Cyclone V device has only M10K blocks, can I assume that "Read old data during write" is not possible in Cyclone V? If yes, what is the alternate solution for this? Looking forward for help.. Thanks. 

--- Quote End ---  

 

 

From what I read it is allowed in cyclone V for certain memory types (single clock or dual...). If in your case it is not allowed then check that you do really mean to read old data & write.  

If that is required by your design then you could change your plan and read just before write by delaying write on same address.
Altera_Forum
Honored Contributor I
36 Views

Thanks for reply.. I need true dual port BRAM with "Read old data while write" option. Read before write by delaying write could have been best option, but since I am migrating from older device to cyclone V, It was already designed to use this option. And modifying the design at this point of time is not feasible. Hence wanted to know if there is any alternate solution for this

Altera_Forum
Honored Contributor I
36 Views

 

--- Quote Start ---  

Thanks for reply.. I need true dual port BRAM with "Read old data while write" option. Read before write by delaying write could have been best option, but since I am migrating from older device to cyclone V, It was already designed to use this option. And modifying the design at this point of time is not feasible. Hence wanted to know if there is any alternate solution for this 

--- Quote End ---  

 

 

One option is using logic to implement ram(if small). 

The other option I can think of is use rising edge to read and falling edge to write so that read is always before write (if timing helps). 

Yu may also check in sim if wr/rd do occur together this could be hard t cover)
Altera_Forum
Honored Contributor I
36 Views

 

--- Quote Start ---  

One option is using logic to implement ram(if small). 

The other option I can think of is use rising edge to read and falling edge to write so that read is always before write (if timing helps). 

Yu may also check in sim if wr/rd do occur together this could be hard t cover) 

--- Quote End ---  

 

 

Thanks for your valuable suggestions kaz. What could be the reason for not supporting this feature in M10K block when it was available in earlier M9K block?
Altera_Forum
Honored Contributor I
36 Views

 

--- Quote Start ---  

Thanks for your valuable suggestions kaz. What could be the reason for not supporting this feature in M10K block when it was available in earlier M9K block? 

--- Quote End ---  

 

 

I think it is to do with silicon level and clocking scheme used around the ram. The actual answer is with Altera and I can only guess. 

Normally - just like a register - one expects a read to read Q before it is updated by D but internally rams do not use clock per each cell (or do not use clock at all except on input/output registers)...
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