I'm having some problems configuring the Triple Speed Ethernet core, working at 1Gbps, with a custom board with 6 transceiver channels (for now I'm trying to use 2 of them) connected to a Cyclone 10 GX. I have a system clock (125MHz) and a dedicated clock for transceiver bank (125MHz). I use Quartus Prime Pro 19.4 (with no license at the moment, which will result in a time-limited sof). My actual configuration is:
I am monitoring some signals from SignalTap: resets are good, pll locked and powerdown signals are ok too, and the most relevant thing is that, for both tse, led_connection_char_err and led_connection_disp_err are toggling a lot, while led_connection_link and led_connection_panel_link are down. Please find some screenshots attached.
Where could the problem be?
P.S. I'm able to use just the Native PHY at 1Gbps (one PHY per channel, whose outputs are shortcircuited-> i'm able to see the ethernet traffic from one side to the other, externally to the FPGA), but when I add the MAC (multirate LLE MAC should be much more simpler to use than PHY) it doesn't work. In addition I didnt' find a way to configure Native PHY with TSE configured as only MAC.
Thanks in advance
As I understand it, you are encountering some issue when using TSE with XCVR in C10GX devices. There seems to be no issue when you are using Native PHY only and performing loopback. However, when you hook up the TSE, you observe issue. For your information, I am currently engaging our TSE expert to provide further assistance. Thanks for your patience.
Yes, exactly. Here attached the PHY configuration, where among two transceiver channels I shortcircuited rx_parallel_data and tx_parallel_data, and rx_datak with tx_datak.
NativePHY IP won't have TSE preset configuration as it doesn't support customized MII, GMII, RGMII or SGMII interface to connect with TSE MAC. This unique feature is provided by TSE IP itself.
I can see that you are setting TSE IP with MAC + PHY serdes interface option.
TSE IP support 2 types of serdes interface in Cyclone 10 GX FPGA (Either LVDS or transcevier)
For LVDS variance (when you select LVDS IO in TSE IP transceiver type). Checkout
For transceiver variance (when you select GXB in TSE IP transceiver type). This is closer to your original intent. Checkout
thanks for your reply.
I checked-out those projects which are a good source of informations.
However, I did not arrange a solution for me.
I'm able to connect two PHYs and see ethernet traffic in these situations:
In the second situation, PHYs have the 10bit tbi interface exposed. Disabling the transceiver option on the TSE, I got the same tbi interfaces (tx_d[9:0], rx_d[9:0], rx_clk, tx_clk). TSE is still configured 10/100/100 MAC + PCS with SGMII bridge enabled. This is the same configuration as in the second example you provided. Obviously the exposed TSEs avalon-ST interfaces have been shortcircuited, but it's not working.
In this situation tse_status_led_connection_link is high (but not the panel_link).
TSE IP itself already contains 8b/10b encoder/decoder so disable the 8b/10b encoder/decoder in NativePHY IP is correct way to go.
>> 1. Earlier you mentioned about a lot of char_err and disp_err issue. Is this issue resolved ?
Now meantime I'm sending packets to the channel, led_connection_link is OFTEN high, until a led_connection_char_err (and consequently a led_connection_disp_err) occurs. Other led_connection_* signals are stable to '0', including led_connection_an (auto negotiation)
>>2.Now you mentioned obviously the exposed TSEs avalon-ST interfaces have been shortcircuited, but it's not working.
>> Can you explain further what do you mean by Avalon-ST intreface is short circuit ? What is short circuit and why are they short circuit ?
I used this therm improperly to indicate that:
tse0.tx <= tse1.rx
tse1.tx <= tse0.rx
where tse*.tx and tse*.rx are the avalon-st interfaces exposed by tse cores. Note that tse*.rx.ready and tse*.tx.ready are always '1'.
>>Is your system setup trying to connect one TSE IP to another TSE IP ? If yes, then you need to configure one TSE IP into PHY mode AN while the other TSE IP into MAC mode AN
My configuration is
pc1<-->| PHY0 <--> TSE0 <--> TSE1 <-->PHY1 | <-->pc2
note that i had to use dots instead of spaces
Ok, I get better understanding on your TSE system setup now. You are basically doing the loopback connection on Avalon ST side instead of external loopback on your board.
In this case, you can separate the debug effort in following sequence.
Good to know issue is resolved at your side.
Alright, I will be setting this case to closure.
Hopefully everything goes well with your project development.