I have a design that uses a CVO. This is in a Stratix III part. The User Guide states that the CVO should be able to run around 271 - 317MHz depending on it's configuration. I'm able to approach this frequency as far as running the chain of IP but when I clock the video out of the CVO Time Quest is telling me a maximum frequency of around 170 - 180MHz. Does anyone have any thoughts on this? I need to run my output clock around 260MHz which I thought I could hit per the User Guide but the tools are telling me differently. Thanks.
did you add the .sdc constraints file for the CVO from $QUARTUS_ROOTDIR/../ip/altera/clocked_video_output? there are some false paths that may help timingcan you paste the first couple failing paths?
You may also want to double check what the maximum output frequency for the I/O standard you are using is in the device data sheet. Some I/O standards may support a much lower frequency than the internal FPGA logic. There may be relevant I/O assignment settings you can change to increase the output frequency.
Hey guys. Thanks for your input. I'll check the constraints this morning. My FAE was in yesterday and he alluded to what Kevin said. This IP was set up for a maximum of 1080p so probably about 148.5MHz. From looking at the Time Quest output he suggested making our own CVO that maybe we could run faster. He thought there was a big adder in the path that could be coded better. So that's the path going forward.I've included a .bmp of the Time Quest output.
I added in the .sdc for the CVO and my worst case slack went from -1.468 to -0.259. So that's quite an improvement. Still not where I need to be but much closer. Sorry the .bmp doesn't show up very well.From Node: tx:InstTx|VipCvo:the_VipCvo|VipCvo_GN:auto_inst|alt_vip_IS2Vid:vipcvo|alt_vip_common_generic_count:v_counter|count To Node: tx:InstTx|VipCvo:the_VipCvo|VipCvo_GN:auto_inst|alt_vip_IS2Vid:vipcvo|reset_counters Is the worst case path.
yeah the bmp came up unreadable, was it resized by the forum?there doesn't seem to be a rule on when you need .sdc files. some get generated in the project directory, some are in the IP install directory, and some are embedded in the core which speed grade SIII and QII version are you using? i'm doing a 1080p design in SIV and i haven't had timing issues. i recommend filing a service request before or in parallel to creating your own CVO
No I resized it. It wouldn't let me upload anything bigger.I did look for other .sdc files and the only ones I found missing were the CVI and CVO. We're in a SIII -3. We have hardware in the field so can't change the FPGA. Currently we're running 1080p without any problems but now we need to run higher resolutions. So far it has not been easy. Also I have not changed over to QII 10.0 yet. I loaded it on another machine and I did get a little improvement in timing there too. Thanks again for your input .
i misunderstood i thought you were targeting 1080p. i know someone going over 1080p as well, i'll ask how they approached the problem. you may need to build a CVO in this caseand i think CVI and CVO are the only VIP blocks with .sdc files, the rest should be in the SOPC .sdc
--- Quote Start --- there doesn't seem to be a rule on when you need .sdc files. some get generated in the project directory, some are in the IP install directory, and some are embedded in the core --- Quote End --- I didn't know there were SDC files to add for the CVI and CVO. I have never had timing problems with them, but I suppose I should be using the SDC files just to be sure. I find it really annoying that the SDC files for generated IP do not automatically get included in all cases. Just yesterday I wasted several hours trying to get a DDR SDRAM controller working until I realized I forgot to include the SDC file. Of course, the solder ball between two of the data pins didn't help either...
Kind of like rock-paper-scissors except solder balls always win.Today I switched over to using the 10.0 tools on another PC. I noticed that the CVO and CVI .sdc files were automatically added to the project - whereas they weren't in 9.0. Another note. I was using the Timing Advisor to increase my FMax. As I added in the recommended options my FMax dropped. I'm sure it all depends on the design but something to keep in mind and not just blindly go with their recommendations.
I also noticed today that the .sdc file for the CVI is added automatically in Quartus II 10.0. I also checked the VIP user guide, and it still indicates you need to add them manually. It only mentions adding SDC files for CVI and CVO, however I searched my install folder and found all of the following:C:\altera\10.0\ip\altera\clocked_video_input\alt_vipcti100_cvi.sdc C:\altera\10.0\ip\altera\clocked_video_output\alt_vipitc100_cvo.sdc C:\altera\10.0\ip\altera\deinterlacer\alt_vip_dil.sdc C:\altera\10.0\ip\altera\frame_buffer\alt_vip_vfb.sdc C:\altera\10.0\ip\altera\frame_reader\alt_vipvfr100_vfr.sdc I didn't try all of the cases, but at least for the frame buffer (VFB), the sdc file is not added automatically.
interesting, so just take the time to check the cores that interface to the outside worldrogerleo: the method used in larger than 1080p video streams was actually multiple 1080p streams stitched together. either way looks like you'll have to write some logic