CXL Type 3 + AXI Reg slice causing system deadlock

[mgiordan]

Hi all,

I'm currently using the CXL Type 3 IP, and am encountering the following issue. Whenever I hook up the CXLIP directly to the MC, things work fine. However, when I place an AXI register slice between the CXLIP and the MC (which in theory should just add a one cycle latency), my system deadlocks when attempting a memory-intensive workload. 

I've used a couple of different AXI Reg slice implementations, including some online, some of my own, and some manual FIFO instantiations. I've narrowed it down to the AW, W, and AR channels (any manager-initiated ones); putting a FIFO on any of these paths causes deadlocks.

I'm pulling my hair out, since I've confirmed that everything is compliant to AXI handshake specifications. Any ideas for next steps would be much appreciated.

[RongYuan]

Hi,

Are you trying to add a delay to the signal iafu2mc_to_axi4?

Regards,

Rong

[mgiordan]

Hi Rong,

Yes, exactly. In essence, we want to perform some manipulation to the AR request. Specifically, we would like to filter out some read requests, and reply with dummy data. However, to implement this demux/interconnect, we need some registers between the connection of cxlip2iafu and iafu2mc, to have time to do our logic. However, whenever I add a register for the AR signal, it seems like we get a bus deadlock. I'm taking care to ensure that we're doing a valid/ready handshake on both sides of afu_top when appropriate, so it shouldn't have any correctness issues.

I'm worried that there's a bug somewhere in the CXLIP or in the AXI to AVMM to MC path, that is only getting exposed when we buffer the AR requests. I think next I will try an open source AXI firewall, or a verification IP, and see if that reports errors.