I'd like to implement a PCIe endpoint using a Cyclone V E FPGA and an external PCIe phy (TI XIO1100).
Looking through an old users guide for Altera's "IP Compiler for PCI Express" it looks like this is a supported configuration, but when I open the PCIe IP compiler in qsys it appears to be impossible to implement PCIe on an FPGA without the hard PCIe core, there's no option to use an external phy.
Is using an external PCIe phy no longer supported by the IP compiler or do I need to upgrade to a different version then the one that comes with qsys? Is it even still sold by Intel, I can't find any info about such an option on the Intel web site.
If anyone can point me in the right direction I'd appreciate it.
Thank you for reaching out.
Just to let you know that Intel has received your support request and I am assigned to work on it.
Allow me some time to look into your issue. I shall come back to you with findings.
Thank you for your patience.
MDIO is a serial interface used to communicate with an Ethernet PHY. I'm trying to interface with a PCI express PHY which is a totally different thing.
PCI express (or PCIe) is a high speed (1.5 Gbit/sec) serial bus that's primarily used by add-on cards in PCs. It's the communication channel that the add-on card uses to communicate with the PC it's installed in.
Some Intel FPGAs with high speed transceivers include a hard IP core for PCIe built in. I'd love to use one of those, but I've had 3000+ Cyclone IV GX parts on order for over a year and have not received any. I'm now getting desperate and trying to redesign my product to use a Cyclone V E part which I do have in stock. That part doesn't support the high speed transceivers, so I'll need to use an external PHY chip.
PCIe PHY chips, such as the TI part I mentioned (XIO1100) use a standard interface to convert a parallel bus to the high speed PCIe serial bus. This interface is called PIPE (PHY Interface for PCI Express). When using such a chip the FPGA still handles the upper level PCIe protocol in a soft IP core and communicates with the PHY chip which handles the high speed serial interface.
The IP compiler for PCIe that Altera provides used to support using an external PCIe PHY chip. I have attached an old version of the user's guide for that IP. Chapter 14 is all about using an external PHY with that IP. The current PCIe IP included with Quartus and Qsys only appears to support parts with high speed transceivers and PCIe hard IP. That IP doesn't help me because the part I'm using doesn't include that hardware.
Is the more compete version of the IP compiler for PCIe still available?
the read access for Cyclone V from an external PHY can be done using the MDIO interface.
Detail you can refer link below
Hope this clarified,
Apologize for late reply,
you can not use the PCI Express Hard IP with an external PHY.
as instead, you can use PCI Express soft IP in order to incorporate an external PHY.
Detail you can refer
Hope this help.
I do a check on Cyclone V device user guide. It is not longer able to support PCIe Soft IP implementation.
There is no workaround for Cyclone V PCIe with external Phy as it does not support PCIe Soft IP.
As instead, you may try to use some old device such as Cyclone IV, III or II (if available)
I do apologize for any inconvenience cause (if have)
Hope this answer your question.
I wish to follow up with you about this IPS case.
Do you have any further questions on this matter ?
Else I would like to have your permission to close this forum ticket
Thanks for your understanding. Apologize for any inconvenience caused.
With that said, I will close this forum ticket from my place.
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