Can not get HDMI IP to output image at 4k 60fps

RonenP · ‎02-03-2021

Hi

I would like to know the following.

For a 4k 60fps the following values are used :

pixel clock : 594MHZ

Total horizontal count : 4400 pixel clocks

Visible pixel count : 3840

Horizontal front porch : 176

Horizontal back porch : 144

Horizontal sync : 88

Total vertical count : 2250 vertical lines

Visible line count : 2160

Vertical front porch : 8

Vertical back porch : 72

Vertical sync : 10

The IP (on Cyclone 10GX) accepts 2 pixels per clock.

what would be the correct clock frequency and count values the IP needs to receive in order to operate correctly at 4k 60 fps.

Another issue I am having is what are the infoframes values I need to set for the IP to operate at a 4k 60 fps, if at all. Does the IP need the info frames in order to output the mentioned resolution.

And last but not least I would like to know what I am suppose to see on the transceiver output of the clock signal since when connecting this line to a scope I do not see a clock signal.

Any help would be appreciated.

Deshi_Intel · ‎02-03-2021

Hi,

Welcome back and fully understand the challenges to work in this COVID pandemic period.

One thing I forgot to mention is HDMI IP max supported video resolution is 4k@p60 with 8 bit per colour (bpc)

Are you using 8 bpc ? Any higher bpc setting will exceed HDMI bandwidth limit unless you lower down the video resolution

Next, Pls see my reply below.

Regarding HDMI IP clocking input

All HDMI clocking calculation can be found in HDMI example design doc (table 14, page 23)
- https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-dex-hdmi-c10gx.pdf
- I also calculated the frequency for you but I guess you miss out my earlier reply in older forum post
- The most crucial clock will be the link_speed_clock (ls_clk) and video_data_clock (vid_clk)
- For your 4k Pixel clock = HDMI TMDS clock = 594MHz
- Then you can basically use the formula shown in page 23/24 to calculate required ls_clk and vid_clk
- ls_clk = TMDS clock frequency/ Symbol per clock = 594/2 = 297MHz
- Assume you are using 8 bit per colour with colour depth factor = 1
- vid_clk = TMDS clock/ Symbol per clock/ Color depth factor = 594/2/1 = 297MHz

Regarding how to transfer video data to HDMI IP

HDMI user guide page 10 (figure 4 and figure 5) will gives you an idea on the difference between 1 or 2 pixel per lock transfer
- https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_hdmi.pdf
- For actual design implementation, you can refer to our example design

Regarding infoframe data transfer via Aux interface

This is question back to your application requirement on how you plan to control the general control packet, video or audio info frame packet
- During normal operation these inputs should be static, and only change if the qualities of the video stream change (such as changing the color depth)
- The HDMI IP Core converts these inputs into Data Island packets and transmits them during Data Island periods
- If these ports are not controlled by the user or tied to 0, the HDMI core will generate default values for these packets compatible with the HDMI Specification 1.4b.
- So you can tie this interface bus input to zero if you have no plan to use them

Regarding no output clock from transceiver channel

Something is wrong somewhere. You should see some clock output
- You can use example design to validate your hardware system
- ensure all FPGA clock, reset and power is supply correctly

Thanks.

Regards,

dlim

JonathanDT · ‎02-04-2021

For the transceiver output clock you need to make sure that you are terminating it to the scope. HDMI is a CML (Current Mode Logic) so many of the HDMI transceivers require a 100ohm differential termination for it to be present.

As indicated those are the correct pixel clock frequencies required for 4k@60Fps. I recommend to get things up and running in this area quickly is a Test Pattern Generator Frame Buffer and then the Clocked Video Out.

Jonathan