Can't simulate EMIF IP for Stratix 10 in ModelSim with generated design example?

[Embeddedesigner]

I have the latest QuestaIntel Starter FPGA Edition-64 2023.2 and I'm trying to simulate a design example for a Stratix 10 by just clicking the simulation box in the EMIF IP to generate a test design example. I'm following the guide "External Memory Interfaces Intel Stratix 10 FPGA IP Design Example User Guide"

After generating the test design example, it gives me the directory that the file is saved under and folder name of emif_userdesign_example_design.

I startup Questa and go to change directory to the ModelSim directory that is saved under the test design example and type in source msim_setup.tcl and it generates a error message in red:

# could not read "../../ip/ed_sim/ed_sim_emif_s10_0/altera_emif_arch_nd_191/sim/ed_sim_emif_s10_0_altera_emif_arch_nd_191_ebuev6a_seq_params_sim.hex": no such file or directory

I can confirm the file does exist. It does not seem like it's able to read it though? How can I fix this to run the design example?

[AdzimZM_Intel]

Hello Sir,

May I know which Quartus* version that you used?

Are you using Windows* or Linux* environment?

I assume you have followed the instruction in this link : https://www.intel.com/content/www/us/en/docs/programmable/683408/21-1-19-2-3/generating-the-emif-design-example-for.html

By default, the an example design will be generated as shown in Figure 4.

The default simulation directory will be at /emif_s10_0_example_design/sim/ed_sim/mentor

Is there any warning or error message while generating the example design?

Can you provide the msim_setup.tcl file in this forum?

Regards,

Adzim

[Embeddedesigner]

I'm using Quartus Prime Pro v. 23.3

and Questa Intel Starter Edition v. 2023.2 to stimulate.

Using Windows 11 OS. 

I am using an updated version of the Document for EMIF, in specific the document updated for Quartus 21.1, IP Version 19.2.3.

According to the Document Revision history, there are no changes associated with simulating the IP, so they are the same.

That is correct, the "The default simulation directory will be at /emif_s10_0_example_design/sim/ed_sim/mentor" 

I've also setup the change of directory information in Questa under File --> Change Directory. 

This is the exact verbatin transcript of the simulation run when I input source msim_setup.tcl

Questa> source msim_setup.tcl
# [exec] file_copy
# could not read "../../ip/ed_sim/ed_sim_emif_s10_0/altera_emif_arch_nd_191/sim/ed_sim_emif_s10_0_altera_emif_arch_nd_191_elybpjy_seq_params_sim.hex": no such file or directory

I've attached the .tcl file for reference and zipped it because the forum won't allow the tcl file upload. 

[AdzimZM_Intel]

Hello Sir,

Let's try to verify the file name.

The .hex file is generated with a random name such as ed_sim_emif_s10_0_altera_emif_arch_nd_191_qlmkdkq_seq_params_sim.hex.

Please verify the bold name is matching.

You can check in the QuestaSim too.

After you have changed the directory to mentor folder, it's will show "cd */mentor" command in the transcript.

Then you can run "cd ./../../ip/ed_sim/ed_sim_emif_s10_0/altera_emif_arch_nd_191/sim/" in the transcript.

Then you run "ls" to list the files inside that directory.

Then verify that the .hex file has similar name to the tcl script.

The tcl script that contains the file location is located in emif_s10_0_example_design/sim/ed_sim/common/modelsim_files.tcl

The file path may located around line 33 in modelsim_files.tcl.

For example at line 33,  lappend memory_files "[normalize_path "$QSYS_SIMDIR/../ip/ed_sim/ed_sim_emif_s10_0/altera_emif_arch_nd_191/sim/ed_sim_emif_s10_0_altera_emif_arch_nd_191_qlmkdkq_seq_params_sim.hex"]"

Regards,

Adzim

[Embeddedesigner · Accepted solution]

Problem is solved.

I had initially used the SystemBuilder, a third party app developed by Terasic to design and synthesize a design incorporating DDR4 memory. This was put on my desktop and design was under the Tools subfolder. I noticed that Questa was complaining that my design was not located in the Quartus Prime Pro directory under my C directory (the terminal indicated false false for c:\intelFPGA_pro\23.3\quartus). So I copied the entire design to this directory, then followed the directions in the Design Example Quick Start Guide for EMIF Stratix 10 FPGA IP to load the design in Questa and everything works fine. Was able to simulate the design.

[AdzimZM_Intel]

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.