FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6445 Discussions

Chaining DMA

Altera_Forum
Honored Contributor II
‎10-02-2012 04:01 PM
963 Views

Hi, 

 

I want to reuse the chaining DMA example. I build a simulation environment for System to Endpoint data transfer using 3 descriptors, 256Bytes in each descriptor. I found a suspicious behaviour of chaining DMA. The programming sequence of DMA is: 

 

BAR2 0x10 = 32'h3 

BAR2 0x14 = 32'h0 

BAR2 0x18 = 32'h00_01_00_00 

BAR2 0x1C = 32'h2 

 

@ Rootport I received a read request of 4*3 DWORDs @ address 0x00_01_00_10. This is strange. I supposed the address should be the base address of Descriptor table (32'h00_01_00_00) that I programmed @ BAR2 0X18. 

 

Thanks 

Ali Umair
0 Kudos

Link Copied

0 Replies
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.