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Clocked Video Input register discrepancy

Altera_Forum
Honored Contributor II
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Had anyone else noticed the discrepancy between the VIP reference design status register (offset 2) for Clock Video Input and the VIP documentation? 

 

The reference design code shows 10 bits with the overflow setter at bit 8 and overflow assert on bit 9. 

 

The documentation says 10 bits but the overflow setter and assert both share bit 9. 

 

Lower bits get offset, so I'm not sure of the signals I can expect from them.
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Altera_Forum
Honored Contributor II
306 Views

It seems like that.

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Altera_Forum
Honored Contributor II
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The VIP documentation is correct.

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Altera_Forum
Honored Contributor II
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Thank you. This matches my own observations of the values. 

 

Just for the archives, this is also confirmed by Altera themselves. The Clocked Video Input class in the VIP Reference Design is out-of-date. Trust the descriptions in the VIP User Guide.
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