Clocked Video Output slave control not functioning

[Altera_Forum]

I have not successfully gotten Clocked Video Output to take dynamic configuration from it's slave port. I can use the wizard to configure it, but none of the 1-14 video modes will configure. 

 Yes, I set them invalid before changing the settings and then make them valid. However, according to the current mode register, it stays stuck at mode 0.

[Altera_Forum]

Hi, 

 I could configure the clocked video output IP of version 8.0 for different modes.   i left the registers for mode 1 untouched. and configured the registers for mode 2 and then set mode-1 invalid and mode-2 valid respectively.  make sure, you are following this order.  - start clock video output IP  - set mode-2 invalid - configure register values for mode-2 -stop clocked video output ip -set mode-1 invalid -set mode-2 valid -start clocked video output IP  hope this would help.  Regards, Foram

[Altera_Forum]

--- Quote Start ---  I have not successfully gotten Clocked Video Output to take dynamic configuration from it's slave port. I can use the wizard to configure it, but none of the 1-14 video modes will configure.  Yes, I set them invalid before changing the settings and then make them valid. However, according to the current mode register, it stays stuck at mode 0.  --- Quote End ---    The mode register will not change until the Clocked Video Output recieves a control packet (on it's Avalon Streaming Video port) that's resolution matches the resolution in one of the configured mode banks. Have you enabled the core and driven video into it?  Also, which version of Quartus as you using? In 8.0 there is a bug in the Clocked Video Output where it selects modes incorrectly. A known example of this is if you configure it for 3 mode banks only banks 1 and 2 will be usable, bank 3 will never be selected. Upgrading to 8.1 fixes this issue.  Gareth.

[Altera_Forum]

Foram, 

 This sequence does not appear to work for me  Am I correct in assuming set functions start with 0? (i.e. 0 is mode 1?) I defensively coded aiming for mode "2", just in case, so I won't care if it's the 2nd or 3rd in the sequence.  My process...  // 3 modes chosen as available in wizard Clocked_Video_Output cvo(CLOCKED_VIDEO_OUT_BASE); while (cvo.get_output_fifo_usedw() == 0) { } cvo.clear_fifo_underflow(); // long pause cvo.start(true); //start cvo cvo.set_valid(2, false); //set mode 3 invalid (or is it 2?) cvo.configure(2); //configure register settings for this mode cvo.stop(true); //stop cvo cvo.set_valid(0, false); //set lower modes invalid cvo.set_valid(1, false); //set lower modes invalid cvo.set_valid(2, true); //set my mode valid cvo.start(true); //start cvo   VidModeMatch register returns 0.  Possible problem. The reference design shows 18 registers per mode, but the VIP User Guide shows 19 registers. I tried it both ways. (At one point it was returning a 4 but I still don't know why) My own data dump of the registers indicates to me it's probably 18. Tons of 1s, followed by some garbage values. The 1s end where 18 registers per mode would end. (18*14+4 registers)  The test pattern generator is generating a 640x480 progressive signal, and I am putting in 640x480 progressive in cvo.configure().

[Altera_Forum]

Gareth, 

 I am using Quartus 8.1. Yes, I'm driving a signal in. I have many objects manipulating the image before it gets to me, though. I will go bypass all of that and just inject directly from a TPG.  Hrm... no, still stuck at mode 0.

[Altera_Forum]

Interestingly enough, the wizard errors out if you configure 14 Runtime configurable video modes. It accepts a 13 value. 

 This implies to me that mode 0 is the wizard defined (read: mandatory) one and is probably registers 4-21. A mandatory mode makes a lot of sense. This still doesn't explain why making it inactive doesn't force a rollover to mode 2.

[Altera_Forum]

--- Quote Start ---  Foram,  This sequence does not appear to work for me  Am I correct in assuming set functions start with 0? (i.e. 0 is mode 1?) I defensively coded aiming for mode "2", just in case, so I won't care if it's the 2nd or 3rd in the sequence.  My process...  // 3 modes chosen as available in wizard Clocked_Video_Output cvo(CLOCKED_VIDEO_OUT_BASE); while (cvo.get_output_fifo_usedw() == 0) { } cvo.clear_fifo_underflow(); // long pause cvo.start(true); //start cvo cvo.set_valid(2, false); //set mode 3 invalid (or is it 2?) cvo.configure(2); //configure register settings for this mode cvo.stop(true); //stop cvo cvo.set_valid(0, false); //set lower modes invalid cvo.set_valid(1, false); //set lower modes invalid cvo.set_valid(2, true); //set my mode valid cvo.start(true); //start cvo VidModeMatch register returns 0.  Possible problem. The reference design shows 18 registers per mode, but the VIP User Guide shows 19 registers. I tried it both ways. (At one point it was returning a 4 but I still don't know why) My own data dump of the registers indicates to me it's probably 18. Tons of 1s, followed by some garbage values. The 1s end where 18 registers per mode would end. (18*14+4 registers)  The test pattern generator is generating a 640x480 progressive signal, and I am putting in 640x480 progressive in cvo.configure().  --- Quote End ---    Hi William,  well, I am using direct address offset and IOWR functions to configure diffenrt output modes. (i am using Quartus 8.0 and VIP suit 8.0. )  I assumed the registers 4-22 are for the mode, configured in SOPC builder, as this was the only way to disable the pre-configured mode.   you mentioned in the last post, that registers 4-21 are for mode1 .. But registers 4-22 are for mode1. So may be you are by mistake using a wrong offset address for setting the mode valid invalid.   IOWR(MY_ALT_VIP_ITC_BASE, 41 , 0); // mode-2 invalid   IOWR(MY_ALT_VIP_ITC_BASE, 23 , 0); // non interlaced  IOWR(MY_ALT_VIP_ITC_BASE, 24 , 640); // width IOWR(MY_ALT_VIP_ITC_BASE, 25 , 480); // height IOWR(MY_ALT_VIP_ITC_BASE, 28 , 12); // Horizontal front porch IOWR(MY_ALT_VIP_ITC_BASE, 29 , 64); // horizontal sync IOWR(MY_ALT_VIP_ITC_BASE, 30 ,144); // HORIZONTAL BLANK IOWR(MY_ALT_VIP_ITC_BASE, 31 , 10); // vertical front porch IOWR(MY_ALT_VIP_ITC_BASE, 32 , 1); // vertical sync IOWR(MY_ALT_VIP_ITC_BASE, 33 , 120); // vertical blank   IOWR(MY_ALT_VIP_ITC_BASE, 41 , 0); // mode-2 invalid   stop(MY_ALT_VIP_ITC_BASE,1);  IOWR(MY_ALT_VIP_ITC_BASE, 22 , 0); // mode-1 invalid IOWR(MY_ALT_VIP_ITC_BASE, 41 , 1); // mode-2 valid  start(MY_ALT_VIP_ITC_BASE);

[Altera_Forum]

Beautiful! I got it working in two tries. 

 Once you confirmed the documentation was correct that there are 19 registers, and not 18, I implemented that and stuck with it.  I was setting back porch values (from the wizard) in the blanking setter functions. Oops. This was causing flicker.  Register number 3 is a hot register with only one bit active at any given time. So it was returning powers of 2 only. I now have my getter take the log_2 of the hot register value to correctly detect the currently active mode.  Yay!

[Altera_Forum]

I have exactly the same problem. I cannot modify any setting. The difference is that I go with PAL / interlaced 720x576. I have tried this: 

  IOWR(VOUT_BASE, 41 , 0); // mode-2 invalid  IOWR(VOUT_BASE, 23 , 1); // interlaced 4  IOWR(VOUT_BASE, 24 , 720); // F0 width 5   IOWR(VOUT_BASE, 25 , 288); // F0 height 6  IOWR(VOUT_BASE, 26 , 720); // F1 width 7   IOWR(VOUT_BASE, 27 , 288); // F1 height 8  IOWR(VOUT_BASE, 30 ,144); // HORIZONTAL BLANK 11  IOWR(VOUT_BASE, 33 , 2); // F1 vertical blank in lines 14  IOWR(VOUT_BASE, 36 , 24); // F0 vertical blank in lines 17 ??????  IOWR(VOUT_BASE, 37 , 23); // first active line 18  IOWR(VOUT_BASE, 38 , 311); // VBI rising edge line in F0 19 ?????  IOWR(VOUT_BASE, 39 , 313); // F1 rising edge line# 20  IOWR(VOUT_BASE, 40 , 0); // F1 falling edge line# 21    VO->stop(false); // stop(VOUT_BASE,1);  IOWR(VOUT_BASE, 22 , 0); // mode-1 invalid  IOWR(VOUT_BASE, 41 , 1); // mode-2 valid  VO->start(); // start(VOUT_BASE);  No luck, nothing happens, the picture on the output is broken. It looks like some syncron problem I have.  When I try to ask what are the current settings, I get a lot '1':  interlaced: 1 active_picture_width: 1 active_picture_height: 1 active_picture_width_f1: 1 active_picture_height_f1: 1 horizontal_front_porch: 1 horizontal_sync: 1 horizontal_blanking: 1 vertical_front_porch: 1 vertical_sync: 1 vertical_blanking: 1 vertical_front_porch_f0: 1 veritcal_sync_f0: 1 veritcal_blanking_f0: 1 active_picture_line: 1 vertical_blank_rising_edge: 1 field_rising_edge_line: 1 valid: 1  It does not matter which mode I try to reach. Even if I dump the whole memory around that address, I get only ones. IMHO this is again some part from Altera what is not documented well at all.  Any help?

[Altera_Forum]

--- Quote Start ---  I have exactly the same problem. I cannot modify any setting. The difference is that I go with PAL / interlaced 720x576. I have tried this:   IOWR(VOUT_BASE, 41 , 0); // mode-2 invalid  IOWR(VOUT_BASE, 23 , 1); // interlaced 4  IOWR(VOUT_BASE, 24 , 720); // F0 width 5   IOWR(VOUT_BASE, 25 , 288); // F0 height 6  IOWR(VOUT_BASE, 26 , 720); // F1 width 7   IOWR(VOUT_BASE, 27 , 288); // F1 height 8  IOWR(VOUT_BASE, 30 ,144); // HORIZONTAL BLANK 11  IOWR(VOUT_BASE, 33 , 2); // F1 vertical blank in lines 14  IOWR(VOUT_BASE, 36 , 24); // F0 vertical blank in lines 17 ??????  IOWR(VOUT_BASE, 37 , 23); // first active line 18  IOWR(VOUT_BASE, 38 , 311); // VBI rising edge line in F0 19 ?????  IOWR(VOUT_BASE, 39 , 313); // F1 rising edge line# 20  IOWR(VOUT_BASE, 40 , 0); // F1 falling edge line# 21    VO->stop(false); // stop(VOUT_BASE,1);  IOWR(VOUT_BASE, 22 , 0); // mode-1 invalid  IOWR(VOUT_BASE, 41 , 1); // mode-2 valid  VO->start(); // start(VOUT_BASE);  No luck, nothing happens, the picture on the output is broken. It looks like some syncron problem I have.  When I try to ask what are the current settings, I get a lot '1':  interlaced: 1 active_picture_width: 1 active_picture_height: 1 active_picture_width_f1: 1 active_picture_height_f1: 1 horizontal_front_porch: 1 horizontal_sync: 1 horizontal_blanking: 1 vertical_front_porch: 1 vertical_sync: 1 vertical_blanking: 1 vertical_front_porch_f0: 1 veritcal_sync_f0: 1 veritcal_blanking_f0: 1 active_picture_line: 1 vertical_blank_rising_edge: 1 field_rising_edge_line: 1 valid: 1  It does not matter which mode I try to reach. Even if I dump the whole memory around that address, I get only ones. IMHO this is again some part from Altera what is not documented well at all.  Any help?  --- Quote End ---    Hi,  i think, you haven't specified all the parameters.   address 28 - horizontal front porch address 29 - horizontal sync address 30 - horizontal blank  and for the vertical parameters, you haven't configured for register 34, 35, 36 , which are specially for interlaced video.   Also, picture is broken as in what ? do you get the video ??  is it that the start of video is not aligned with the screen ? you can adjust it in the TV encoder chip by adjusting registers for start of active video, horizontal position register, vertical position registers.

[Altera_Forum]

Hi, 

 Thank you for your answer.  ... you haven't specified all the parameters.  address 28 - horizontal front porch address 29 - horizontal sync address 30 - horizontal blank  and for the vertical parameters, you haven't configured for register 34, 35, 36 , which are specially for interlaced video.    It is not needed to specify these parameters if I use embedded syncs. And with embedded syncs there is no chance to adjust anything at the video encoder, not to mention, that is unnecessary.  Broken means broken :-)) How can I specify.... So the picture is aligned well, but the inside part like a Picasso picture and everything is changing.  So, I still don't have diea how can I read the registers, then after this how can I set them. Any help is greatly appreciated!

[Altera_Forum]

Oh Sorry. I assumed, you are using separate sync signals and not embedded with video.  

 Currently i don't have the development board to verify the clocked video output behavior.  But may i ask, from where does this PAL video comes and what is the pixel clock and how is it generated.   Just a suggestion, you can verify the altera avalon ST video control packets preceding the video frame and verify the resolution and format.

[Altera_Forum]

The application is very-very simple. There is no external source. The source is a Test pattern Gemerator with approriate parameters (720x576, YCbCr, 4:2:2, 8 bit wide, sequence, interlaced). Just two componets are in the NIOS, this pattern generator, and the Clocked Video Output which has these parameters: 

 720x576, 8 bit, numof CP 2, sequence,, Interlaced, Emb. in video., PAL template is apllied, btw. Use control port is checked on, BUT I STILL DON'T HAVE ACCESS to the parameters in runtme.

[Altera_Forum]

I hope the number of runtime configurable modes in clocked video ip is set to atleast 3 or more than that.  

 and which is the clock to the clocked video output IP as pixel clock?

[Altera_Forum]

Of course 27MHz

[Altera_Forum]

If you mean to the inside clok that is 100 Mhz, the same as the CPU clk.

[Altera_Forum]

i meant, from where does this clock comes ?

[Altera_Forum]

For both clocks (inside for NIOS and for pixel clock) comes form external sources (50 Mhz osc) trough 2 pieces PLLs. Cyc3 dev kit board, btw... 

 The clock are very stable, with very-very small jitter. 1 have GHz scope with many channels...  Thank you for youyr effort trying to help me!

[Altera_Forum]

i am talking about the pixel clock to the clocked video IP. 

I am not sure which board you are using to test this clocked video IP but it will go through the TV encoder chip before coming to the TV display.  The decoder chip might have a output display modes. e.g the ch7010 on 3c120 board has few modes for PAL output and for 720x576 has 882x625 as actual resolution and thus clock will be 27.562500 MHz.   and for proper pixel clock synchronization, you will need to run this TV encoder chip in master clock mode and use the output clock from this TV encoder chip as a pixel clock to the clocked video output IP.   i am not sure about the values of registers in clocked video IP , as i never actually read back to check the value. and currently dont have development board to verify, as i mentioned earlier.   But if its the pixel clock because of which, your output video looks broken (??) . then this might be the reason.

[Altera_Forum]

This is not my first video project, I deal with such stuff now for 10 years, and also helped to well known chip maker companies in some chip development too, so I believe I know a lot about the encoder chips and the standards, resolutions. 

 But talking about the concrete problem... The encoder chip I use is my labor encoder and is used now for many years for different source testing, and of course it works with any other source.   882x625???  The active pixel resolution is 720x576 by the ITU BT or CCIR 601. Together with H blanking pixels is 864 (1728 bytes with TRS). V resolution is 625 (inc. VBI lines).  1728 x 625 x 25 (full frame == 50 interlaced) = 27 000 000, so that 27 Mhz.

[Altera_Forum]

Oh i am not very experienced in the video projects. So i might not be very expert in giving solutions.  

 But have worked on the 3c120 development board and got the TV output working. And while working on this project, i came accross the problems which i found similar to your posting. So suggested the solutions, which i thought, you would find useful.   anyways, i know for 720x576 active resolution, as per the standard, its 864x625 and thus 27 MHz.  But i was telling about the TV output mode(mode 22) on CH7010d (Bitec Quad video board), which has 882x625 as actual resolution.   but i think, you would be able to find solution for this particular board and problem better than me. all the best!