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Color Plane Sequencer causing video back pressure (I think)

Smith222122
Beginner
272 Views

Hello there,

Below is an outline of my video stream path:

SDRAM (1920 x 1080) -> Frame Reader -> Color Plane Sequencer (CPS has two outputs) ->.....

1st output from CPS

-> Clocked Video Output -> DisplayPort IP -> XCVRS..... to DisplayPort sink

2nd output from CPS

-> Scaler (down scaler to 1280 x 800) -> Clocked Video Output -> SERDES ->..... to LCD screen

 

The issue I am seeing is screen flicker on the LCD screen whenever I add the DisplayPort video output. Specifically, when I only have one output from the CPS to the LCD screen, the video displays fine. When I add a second video output from the CPS, my LCD screen starts to flicker. 

 

The DisplayPort video lane requires a lot more video data. I think this is causing back pressure over the Avalon-ST interface. The DisplayPort video lane is running at 4 pixels in parallel, while the LCD is running with only one pixel in parallel. The video data read from SDRAM into the Frame Reader to the color plane sequencer is uniform until it enters the CPS. That's where the CPS changes the DisplayPort video path to output 4 pixels in parallel. The LCD screen remains only 1 pixel in parallel. Only 1 pixel in parallel is read from SDRAM.

 

Therefore, the CPS needs to wait for additional pixels before it has valid output for the DisplayPort video lane. I am afraid this waiting is causing back pressure in both video lanes causing my LCD screen to flicker?

 

Can anyone think of a solution to this that does not require two completely seperate video paths (and hence frame readers)? I am using the CPU in my design for the SDRAM controller and to run my application software. I don't have enough CPU bandwidth to add another frame reader and SDRAM controller.

 

Thank you!

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2 Replies
ZulsyafiqH_Intel
Employee
120 Views

Hi Smith,


Good Day.

Thank you for your patience.

Due to some the technical error, we have just receive your question.


May I clarify the video format first? Based on the EIA/CEA-861 standard.

and also the Color Plane Sequencer II Parameter Settings?


Thank you.


Best Regards,

ZulsyafiqH_Intel




ZulsyafiqH_Intel
Employee
92 Views

Hi Smith,


We do not receive any response from you to the previous reply that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread.


Thank you.

Best Regards,

ZulsyafiqH_Intel


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