Compatibility

[Altera_Forum]

Before I upgraded to 7.2, I used 5.1. I really like the interface for FIR megacore function. However, now that I upgraded to 7.2, all the interface is changed to AST interface.  

 How do i connect it the same way I have before?   In 5.1, I have these connections: 1. clk 2. rst 3. data_in 4. fir_result 5. done 6. rdy_to_ld  In 7.2, I have these connections: 1. clk 2. reset_n 3. ast_sink_data 4. ast_sink_valid 5. ast_source_ready 6. ast_sink_error 7. ast_source_data 8. ast_sink_ready 9. ast_source_valid 10. ast_source_error  how do I make these new connections from 7.2?  if not, can I use Quartus 7.2 with IP Megacore Library 5.1 to bypass all these AST interface?  THANKS!!!!

[Altera_Forum]

Hello, 

 separately installed Megacore components, e. g. FIR compiler, should be still accessable (if not deinstalled), the are highlighted in the Megawizard IP selection.   Apart from that, you should be able to write a wrapper to convert the old to new interface, but I'm not familiar with FIR compiler.  Regards, Frank

[Altera_Forum]

I was able to use the older version of FIR. 

  However, has anybody implemented the FIR from 7.2 yet?  thanks!!!

[Altera_Forum]

I've used the Fir in 7.2 and has no problem. 

Try to have a look at the help. Moreover: clk: it's the same clock of your previous Fir  reset_n: it's active low so you've to put a not before your reset signal  ast_sink_data and ast_sink_valid are the input to the FIR Block  ast_source_ready: must be set to 1 if the block that take the FIR Block output can accept it (for example if you store the output of the fir to a Fifo you should use the NOT FULL of the fifo).  ast_sink_error: useless fix it to ground (or connect it to the ast_source_error of the block that feeds the input to your Fir).  ast_source_data & ast_source_valid: are the output data and valid of your fir block  ast_sink_ready: it's an output that indicate that the fir is able to accept new datas  10. ast_source_error: reveal if your fir has problems  Keep in mind that the new way of the IP is that all of them could be cascaded with easy and that than connect to an avalon bus also (it's from that, that they take their strange name).  Moreover try to use the graphic approac (Block Editor) and put down a Fir so it'll become more easy to understand what they're for. Pay attention to the notation of source and sink that imo are done very bad cause they refer to different things also with the same name. For example ast_source_ready is an input that indicate that a block following your one is ready to accept data and so your block could send data out to it.

[Altera_Forum]

The FIR core now follows the Avalon ST interface spec. You can seperate the whole interface into two parts, one is sink, one is source. Sink_* interface is used to accept the data from Source_* interface. Other signals are as following: 

 sink:  valid: input: means the data is valid  ready: Output: means that the core is ready to get the data or not. You should keep valid signal low if this signal is not high. otherwise the core can't accept any data.  SOP: start of the packet, this is used when you are dealing with the multipler channels design. SOP means channel 0 data. and EOP means the last channel data.  Source side will be the completely reversed as the sink part.