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Confusion with Altera Soft LVDS Parameters- PLL setting

Hi,

I'm trying to use Altera Soft LVDS IP core in TX mode with internal PLL. I'm confused with the parameter Data Rate, under PLL setting. Is it the data rate of incoming parallel data to the LVDS or output data rate of serial data going out of LVDS?

as per the LVDS userguide https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_lvds.pdf

page 46 table 12 it Specifies the data rate going out of the PLL. please enlighten me.

 

Thank You very much

 

 

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Employee

Re: Confusion with Altera Soft LVDS Parameters- PLL setting

Hi ,

The data rate is specified for the IO pins ,

kindly find the data rate specification in data sheet from table no;36

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/m10_datasheet.pdf

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Employee

Re: Confusion with Altera Soft LVDS Parameters- PLL setting

Hi ,

Let me know if you need further assistance.

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