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Altera_Forum
Honored Contributor I
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Controlling TLP attributes ... for PCIe tranasctions

For the Hard or Soft PCIe IP used by Altera, How can I control attributes in the TLP header ie  

 

- RO, IDO, Hint bits, BDF control, AEarlyWrResp control etc. 

 

I hope the answer isn't that I need to write the IP from scratch ....  

 

Thanks in advance, Bob.
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Altera_Forum
Honored Contributor I
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Altera factory says to use Avalon-ST instead of Avalon_MM ... any ideas on this ? I believe I need to provide part of the PCIe stack with AVALON-ST which is much more work than I was figuring ... having said that .. if Avalon-ST is the only solution .. I will investigate and size it and make the call. 

 

Best Regards, Bob.  

 

PS: I'm attempting to provide some similar functions available in commercial PCIe Exerciser cards at a fraction of the price ... I know they use Altera FPGA's and will be successful if I can simply control the TLP attribute bits say from NIOS II code.
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