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Could Modular SGDMA perform ping-ping operation when just two descriptor is written?

Altera_Forum
Honored Contributor II
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First,sorry for a duplicate thread.I posted a thread in NIOS forum wrongly yesterday,and I don't know how to move it here. 

 

I use Modulat SGDMA with PCIe IP to transfer video frame from FPGA to Our Soc.We want to perform a ping-pong operation to write video frame to two different address of Our SOC.The 1st frame is to be written in addr A,the 2nd frame is to be written in addr B,the 3rd frame is to be written in A,and so on.In modular SGDMA,it has a "park write"bit,but when I construct two descriptors with "PARK WRITE" bit is enabled in each descriptor,I assume the descriptor chain will be used again and again.But When I access DMA CSR register to see which descriptor is operated in ISR,it seems that always the last descriptor is operated,the first descriptor is not performed again. 

Can Modular SGDMA to perform ping-pong operation with descriptors chain is just one-time written?
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