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Critical Warning (10169) on DDR2 ALTERA IP

Altera_Forum
Honored Contributor II
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I'm using Altera's DDR2 IP to control DDR2 memory. 2 critical warnings as below pops out after compilation. The warnings are pointing to the code that ALTERA provided for DDR2 control.  

I don't konw why these 2 warnings pop up with "critical level". Should I do something to resolve these warnings and how? or just leave them as it is? 

(The attachment is my project files)  

 

 

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Critical Warning (10169): Verilog HDL warning at alt_mem_ddrx_controller.v(508): the port and data declarations for array port "afi_rrank" do not specify the same range for each dimension 

Critical Warning (10169): Verilog HDL warning at alt_mem_ddrx_controller.v(509): the port and data declarations for array port "afi_wrank" do not specify the same range for each dimension 

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Altera_Forum
Honored Contributor II
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Dears, i found answer from Altera's website(see link below). It said it's a bug of quartus ii of earlier version than 12.1. And users can ignore these 2 warnings. 

http://www.altera.com/support/kdb/solutions/rd08152012_590.html?gsa_pos=2&wt.oss_r=1&wt.oss=verilog%20hdl%20warning%20at%20the%20port%20and%20data%20declarations%20for%20array%20port%20do%20not%20specify%20the%20same%20range%20for%20each%20dimension
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