FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5950 Discussions

Critical Warning (10169) on DDR2 ALTERA IP

Altera_Forum
Honored Contributor II
809 Views

I'm using Altera's DDR2 IP to control DDR2 memory. 2 critical warnings as below pops out after compilation. The warnings are pointing to the code that ALTERA provided for DDR2 control.  

I don't konw why these 2 warnings pop up with "critical level". Should I do something to resolve these warnings and how? or just leave them as it is? 

(The attachment is my project files)  

 

 

--- Quote Start ---  

Critical Warning (10169): Verilog HDL warning at alt_mem_ddrx_controller.v(508): the port and data declarations for array port "afi_rrank" do not specify the same range for each dimension 

Critical Warning (10169): Verilog HDL warning at alt_mem_ddrx_controller.v(509): the port and data declarations for array port "afi_wrank" do not specify the same range for each dimension 

--- Quote End ---  

0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
104 Views

Dears, i found answer from Altera's website(see link below). It said it's a bug of quartus ii of earlier version than 12.1. And users can ignore these 2 warnings. 

http://www.altera.com/support/kdb/solutions/rd08152012_590.html?gsa_pos=2&wt.oss_r=1&wt.oss=verilog%...
Reply