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Honored Contributor I
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Cyclon IV E - PLL IP - Dynamic Phase Shift

Hello, 

 

I've created the IP PLL in Cyclon IV E, that works in itself - to output 25MHz and 100MHz clocks. 

 

I've written a code to be able to phase shift both of these clocks - by using as basis one of Altera's examples for a different FPGA. I've modified the State Machine a little bit - one the controls the Phase Shift in the PLL IP. 

 

Made it so that when a user writes by I2C to a register - which contains - 1 bit of telling PLL IP if phase is up or down; 1 bit - to choose the counter out (I suppose the 25M/100M); 4 bits to control number of steps. 

 

However, I do not get any response when I do the writings in the phase of any clock.. I've uploaded the State Machine and the PLL IP code, as well as the connection in the main code, hopefully you could advise what may be the problem. 

 

 

the PLL IP - "PHASE_PLL_100M_To_25M.vhd" 

The State Machine - "SHIFT_PLL_SM.v" 

 

the code fragments that connect these blocks: 

 

 

// To control the phase shift SM - to toggle the phase shift back to '1' after shift 

always @ (posedge clock10m or negedge reset_n or posedge sequence_done)  

if (~reset_n) 

toggle_phase_shift <= 1'b1; //set phase shift to '1' - phase shift SM in "reset" 

 

 

else 

if (sequence_done == 1)  

toggle_phase_shift <= 1'b1; //set phase shift to '1' - back after phase shift has occured 

 

 

else  

toggle_phase_shift <= (i2c_wr_valid_s & i2c_reg_addr == 32'h34) ? 1'b0 : toggle_phase_shift; 

 

 

 

 

 

PHASE_PLL_100M_To_25M dram_core_pll ( 

.areset (!reset_n &nbsp;), //input, global reset 

.inclk0 (clock66m &nbsp;), //input clock 66.666MHz 

.c0 (FP_PLL1_100M_CK_P), //output clock 100MHz synced to 66.666MHz 

.c1 (FP_PLL2_25M_CK_P), //output clock 25MHz synced to 66.666MHz 

.phaseupdown (phase_updown), 

.phasecounterselect (phase_clkslct), 

.phasestep (phase_en_wire), 

.phasedone (phase_done_wire), 

.scanclk (clock10m) 

 

 

); 

 

 

SHIFT_PLL_SM shift_pll_sm ( 

 

 

.clk (clock66m), //input clock 66.666MHz 

.reset (toggle_phase_shift), //'0' starts the SM, default is '1' 

.phase_en (phase_en_wire), //enable phase shift from SM to PLL 

.phase_done (phase_done_wire), //phase done signal from PLL to the SM at end of a phase shift 

.num_of_steps (num_of_steps), //num_of_steps of phase shifts  

.sequence_done (sequence_done) //as sequence_done goes to '1', "reset" should go to '1' to wait for next user toggle to '0' 

 

 

);
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