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Valued Contributor III
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Cyclone 4GX DMA Controller - Read Address register truncation?

Hey everyone, 

 

I'm following Chapter 26 of the Embedded IP guide (DMA Controller). I've build a PCIE controller, DMA controller and onchip ram for a project I'm working on. My goal is to DMA from the ONCHIP ram into the host memory. I'm an experience PCIe driver developer, but the FPGA DMA controller from altera is new to me. 

 

I'm attempting to write to the read/write address of the DMA Controller register map (in my case on bar2 offset 0x4000). 

 

From my Linux driver I can successfully read/write from/to the onchip ram in my design (bar0) but attempts to set the read/write address of the DMA controller registers (to dma onochip ram back to a PC host), result in the write address being truncated. 

 

For example: 

 

Here's some debug from my Linux driver, showing the virtual and physical addresses of a dma buffer I've allocated in the host. The physical address of the buffer is dma addr 0x2774e000 length 0x1000 bytes. 

 

I write 0x2774e000 to the dma controller writeaddress register (then read it back), and it's one 21 bits long, 0x00004004 = 0x0034e000. SUbsuently, when I start the DMA controller, I do get interrupts but no data is being transferred. 

 

[ 6298.939612] drv_buffer_alloc allocated buffer addr 0xe4bb01a0 

[ 6298.939615] pci_cpu addr 0xe774e000 dma addr 0x2774e000 len = 0x1000 

[ 6298.939688] 0x00004000 = 0x00000002 

[ 6298.939691] 0x00004004 = 0x0034e000 

[ 6298.939694] 0x00004008 = 0x00000000 

[ 6298.939698] 0x0000400c = 0x00001000 

[ 6298.939701] 0x00004010 = 0x00000000 

[ 6298.939704] 0x00004014 = 0x00000000 

[ 6298.939707] 0x00004018 = 0x0000039c 

[ 6298.939718] 0x0000401c = 0x00000000 

 

It feels like the issue is related to the size of the bar translations I have set up (the defaults came from the altera guides), like it drops the upper bits above 21st bit and is truncating my physical write address. 

 

The problem is, how are we expected to DMA from the FPGA into a host allocated 32bit DMA buffer? The documents don't cover this, or don't cover this well, or I've yet to discover that specific document. Feels like I don't understand the Address Translation well enough, but the documents are difficult to comprehend from a driver developers perspective (who's used to building PCIe drivers for may other commercial controllers). 

 

Any thoughts? 

 

Thanks, 

 

- Steve
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Valued Contributor III
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--- Quote Start ---  

 

Any thoughts? 

 

--- Quote End ---  

 

 

... answered my own question, thought someone else would benefit... 

 

I can't post a link to the forum post that helped (sigh) but if you search for "dma controller write address" or article 39259 you'll find it. Looks like I needed to set the qsys PCIE Controller address translation to 32bit (up from 21bits), switch from dynamic to fix translation and move the pcie txs memory mapped slave to 0x80000000, to avoid overlapping with the on-chi-ram. 

 

This works, I can now DMA on-chip-ram to a host allocated buffer. 

 

Sorry for any noise.
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Valued Contributor III
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--- Quote Start ---  

I can't post a link to the forum post that helped (sigh) 

--- Quote End ---  

 

 

Looks like I've now passed the magic 5 post limit, so here's a direct link for anyone with the same issue: 

 

http://www.alteraforum.com/forum/showthread.php?t=39259&highlight=dma+controller+write+address
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