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Altera_Forum
Honored Contributor I
861 Views

Cyclone V GX Dev Board DDR3 Timing Violations

I have been having "Hold Violations" in my Qsys soft DDR3 controller for the Cyclone 5 GX development board. 

 

I get a negative error slack value on the *|pll0|pll2_phy~PLL_OUPUT_COUNTER|divclk 

There are 4 others that also give negative slack (*|pll0|pll ... PLL_OUTPUT_COUNTER|divclk) 

 

I set all the clock global clocks with the assignments editor (inst|ddr3|pll0* Gloabl ... ) with no success. 

I set multi-corner analysis on. -no change 

 

What finally made the hold violations go away was "set_min_delay" commands in the .sdc file. 

 

Here is a list of the commands I used: 

set_min_delay -to [get_clocks {inst|c5gxfc7_fpga_bup_qsys_inst|ddr3|pll0|pll1~PLL_OUTPUT_COUNTER|divclk}] -2.000 

set_min_delay -to [get_clocks {inst|c5gxfc7_fpga_bup_qsys_inst|ddr3|pll0|pll1_phy~PLL_OUTPUT_COUNTER|divclk}] -4.000 

set_min_delay -to [get_clocks {inst|c5gxfc7_fpga_bup_qsys_inst|ddr3|pll0|pll2_phy~PLL_OUTPUT_COUNTER|divclk}] -4.000 

set_min_delay -to [get_clocks {inst|c5gxfc7_fpga_bup_qsys_inst|ddr3|pll0|pll6~PLL_OUTPUT_COUNTER|divclk}] -3.000 

set_min_delay -to [get_clocks {inst|c5gxfc7_fpga_bup_qsys_inst|ddr3|pll0|pll7~PLL_OUTPUT_COUNTER|divclk}] -3.000 

set_min_delay -to [get_clocks {clkin_50}] -1.000 

 

As another experiment, I could also use the "set_false_paths" to make the Hold violations go away... 

 

set_false_path -to [get_clocks {inst|c5gxfc7_fpga_bup_qsys_inst|ddr3|pll0|pll1_phy~PLL_OUTPUT_COUNTER|divclk} ] 

 

My testing procedure was as follows: 

 

1. Do an "Analysis and Synthesis" in Quartus 

2. Pull up the TimeQuest Timing analyzer 

3. Create the Timing netlist with Post-map checked 

4. Read the SDC File and Update Timing netlist 

5. Check the Report Hold Summary and other summaries 

6. Make changes to my sdc files, Reset the Design, Read the SDC File, Update Timing Netlist, then check my Reports again until I got the results I think I wanted. 

 

I am new to FPGA design, and I was hoping somebody could explain to me what I did and what might the concequences be of doing what I did. I was also wondering if the settings apply to the real hardware, or just simulation results? 

 

I hope my experiments help others, and any expert analysis of my procedures would be greatly appreciated. 

 

Thanks, Ed 

 

 

 

 

 

 

set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to *ddr3|pll0|pll* 

set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to ddr3_clk_n 

set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to ddr3_clk_p 

set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to ddr3_dqs_n[0]_OUT 

set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to ddr3_dqs_n[1]_OUT 

set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to ddr3_dqs_p[0]_OUT 

set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to ddr3_dqs_p[1]_OUT 

set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to ddr3_dqs_p[0]_IN 

set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to ddr3_dqs_p[1]_IN 

set_instance_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION_FOR_NON_GLOBAL_CLOCKS ON -to inst|c5gxfc7_fpga_bup_qsys_inst|ddr3 

set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
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Altera_Forum
Honored Contributor I
77 Views

My next step in the process was to do a full compilation. To my surprise, and a half hour later, my design was full of more timing violations. This time, mostly setup violations. I again went to the Timequest timing analyzer, created a netlist (post-fit), and repeated my procedure of adding commands to my sdc file. This time, I added mostly "set_max_delay" to the clock signals that were showing setup timing violations. After fixing the timing violations, again, I did a full compilation. This time it compiled with no violations. 

 

I still feel totally insecure with the design I have built. The compilation says I have 8 critical warnings, and 178 other warnings, but compilation was a success.?! I get .sdc file warnings about clocks that could not be matched with a clocks, ignored set false paths, overwriting existing clocks, ignored set_clock_uncertainty, things that could not be matched with a pin, empty collections, the fitter compensating PLL clocks, dqs assigned different I/O standards, and a ton of other stuff I have no idea what is means. Sometimes I look up the errors and I find that the Altera knowledge base says I can ignore these warnings. Really?  

 

Altera - com' on man! Make this better.
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