I've generated PLL and PLL_reconfig function with Quartus18.1.
The PLL receives 20 MHz and sends out 25 MHz. I want to change the frequency of the outcoming signal from 25 MHz to 50 MHz.
I'm new with CycloneV and with Quartus18.1
# ** Error: (vcom-7) Failed to open design unit file "C:/Alex/my_designs/18_1/PLL_reconfig/PLL_reconfig_001/cycloneV/PLL_RECONFIG_20_25.vho" in read mode.
# No such file or directory. (errno = ENOENT)
Indeed, there is no such a file. But I have get PLL_20_25.vho for Altera PLL Mega-Function, and PLL_RECONFIG_20_25.hdl for Altera PLL Reconfig Mega-Function. Why file . vho doesn't generate for Altera PLL Reconfig Mega-Function?How can I control it? When I'm trying to simulate the design via Model-Sim10.5B, then no waveform generated by Altera PLL before reconfig and after reconfig.
thank you for your replay.
I've simulated my projects (include PLL dynamic phase shift) via Native-Links many times .
The question is another: in order to simulate via Native-Link , Quartus shall produce xxx .vho file for Altera PLL Reconfig Mega-Function.
But it doesn't.
The file xxx.vho Altera PLL Mega-Function has been generated Instead.
why? Is it wrong? How can simulate frequency reconfiguration on CycloneV?