PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
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Having an application with NIOSII, DDR HP Controller and others, all are running the same ddr_sysclk at 133MHz. Using Quartus8.1, CycloneIII and the basic application works with single accesses to DDR. Now we are trying to use the DDR burst capability in order to get over the Latency time. We'we tried a Avalon Pipline Bridge with bursts enabled with no success, the reads and writes to succesive addresses are still dispatched as single accesses. Does anybody have expirience in using bursts???? Our DDR is a single 16 bit device and all accesses from NIOS are 32bit. Thanks MKopo
1 - Bursting is enabled on its bus masters 2 - Data access is performed via the cache. The pipeline bridge will only add latency. If you don't need it to meet timing requirements, remove it. Jake
use Q9.1. The new HPCII controller will group transactions to create bursts automatically, so there is no need to enable bursts on the processor or sopc builder side.
