I am trying to run DDR DRAM using an HPCII. I have Quartus II V10.0 SP1, and a Cyclone III FPGA. My DRAM initialises, calibration is successful and local_ready goes high, both in simulation and on the real board. If I then start to use the DRAM controller to write to the DRAM then the simulation runs fine and I can see writes to the DRAM model. However, on the real board, I get a few hundred or a few thousand writes and then local_ready from the DRAM controller stays low. This happens even if I use constant value address and data. If I vary the address then the length of time the controller works before local_ready sticks low seems to depend on what sequence of addresses I use. For some sequences of addresses I continue to get local_refresh_ack going reqularly every 7us or so, and I see RAS and CAS being generated to the DRAM on the board. But in all cases I can't use the DRAM any more as local_ready stays low.Has anyone any suggestions as to what it going wrong? As I am simply issuing writes, I am not dependant on the actual DRAM working properly. So something seems to be upsetting the DRAM controller, but it must be working reasonably well as calibration completes successfully.
Altera support pointed me at an Altera Wiki entry entitled "Local ready signal issues with Altera external memory controller IP".This tells me that "A common issue with the local_ready signal is it permanently goes low preventing any further commands from being accepted by the controller, effectively resulting in the controller being "locked up"." The DRAM controller has a variable "proper_beats_in_fifo", and if I monitor this and ensure it doesn't reach it's max value by holding off writing to the DRAM at regular intervals, then the local_ready signal doesn't go permanantly low and the controller doesn't lock up.