DDR2 Ctrl compile error:Cannot find source node 'ddr2_dqs[0]_in

[Altera_Forum]

When I compiler my project based on Altera's Dev Kit's solution:an431 with changes as follow:instantialized two ddr2 sdram controller,one on the top side,and another on the bottom side,each of them is 32bit wide,in the progress of compilation,enfronted the following error: 

 Error: Cannot find source node 'ddr2_dqs[0]_in' Info: The most likely cause of this type of error is: Info: (1) Some signals on the local-side interface are not connected causing logic to be optimised away, Info: This script requires that the complete logic for the specified width of the datapath (both read and write paths) be present in the design. Info: (2) The clear-text HDL files for the datapath may have been modified. Info: (3) Not all clocks from the system pll are global.   I am sure that the local-side interface are connected correctly and that The clear-text HDL files for the datapath not be modified, so I wonder what the info3 meaning? Anyone can help me to solve this problem?

[Altera_Forum]

Did you create one controller and instantiate it twice, or physically go through the megawizard and create two separate cores? I would suggest making two separate cores, as there are scripts that search through the design for signals, and if it finds them twice, it may have difficulties resolving them. (I'm not sure if this is your problem, but just a suggestion.)

[Altera_Forum]

perhaps that is the problem. 

evenhthough I have create two seperate core through the megawizard,but each of them have the same interface.

[Altera_Forum]

If they're physically two separate cores(two names, two sets of files, two sets of Tcl files for doing constraints), then that's not the problem. Since you have the base case that works, I would look for that specific node and see what it is. Then look for it in the two other cores and see if it exists.