FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6359 Discussions

Ennumeration in Mesh connected PEX Switches (PEX8648)

Altera_Forum
Honored Contributor II
920 Views

hi, 

we are planning to design boards which are compliance to vita46.4 (pci express on vita46). each board will have four mpc-8641d (dual core ppc from freescale. (refer: http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=mpc8641d&fsrch=1 (http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=mpc8641d&fsrch=1)). each processor has two x8 pci express link. one x8 link from each processors will be connected to a on board pex-8648 (totally 32 lanes for processors). and the remaining x16 of pex-8648 will be connected to the vpx backplane as per the vita46.4 standard. please refer the connectivity chart in the backplane datasheet which is available in the following link for better clarity about the backplane interconnections(http://www.bustronic.com/switchfabric/vpx_6u.html (http://www.bustronic.com/switchfabric/vpx_6u.html)). that backplane contain 5 vpx slots which are connected with each other in a mesh topology.  

now for this discussion assume that the backplane contains only 3 vpx slots which are interconnected to each other with x4 pci express link as shown below.  

slot1<---x4--->slot2<----x4----->slot3<----x4----->slot1  

(first slot1 & the last slot1 is referring to a single physical slot).  

now let us assume that the processor in the slot1 is acting as host and start enumerating other devices in the whole system. due to this mesh connection, the processor in 'slot1' can communicate with devices in 'slot3' in two ways.  

1. through the direct connection between 'slot1' and 'slot3'  

2. redundant path through 'slot2' (enumerate the switch in 'slot2'. then through this switch enumerate the devices in 'slot3').  

query:  

1. how the pci express host in the slot1 know that the devices in the 'slot3' was already enumerated when it is seeing the devices in the 'slot3' through the redundant path.  

2. being a tree architecture bus whether pci express will handle this situation?  

3. is there any design precautions to be taken in this scenario?  

may be there will be provisions in the protocol to handle these types of scenarios. but we need to make sure that this topology will work. please clarify the above points.  

thank you for your patience to read this long mail. i have no other way to cut short the message.  

regards,  

thomas c.n
0 Kudos
0 Replies
Reply