DDR2 Ctrl compile error:areset signal must be configures as clear but now as none

[Altera_Forum]

I have use the MegaWizard to generate the DDR2 sdram controller V7.2, and compiled it successful seperately, but when I intergrate it in my own design,there is a compile error: I/O atom "dqs" ddr_dqs uses post-amble circuit---ARESET signal must be configures as clear but now as none. 

 Why?

[Altera_Forum]

Most likely you did not connect the reset signal of DDR2 controller correctly to your own design.

[Altera_Forum]

I believe what is happening is that not everything is fully connected up. This results in quartus optimising things away. It then gets to the point of recognising that various items have been declared (such as the post-amble on the bi-directional dqs signal.) However, it has optimised away enough of the circuit that the dqs is no longer bi-directional. That is, the read section of the bus has been optimised away leaving on the write (or output) section. Quartus then issues an error because things no longer match up. 

You are probably getting the reset error because the read side of the DDR2 SDRAM controller has been optimized out. The read path for the DDR2 SDRAM controller will be optimized out if the controller themselves are not getting its required clocks or resets. The optimization will also occur if the rd_data and rd_valid signals of the controller are not connected up to anything.   Common causes of this are things like   1) Half (or more) of the local data bus is not connected … most likely the read.  2) Core requires a dedicated resynch clock and one has not been wired up  3) Read request is tied low.  4) Add constraints has not been applied

[Altera_Forum]

--- Quote Start ---     Common causes of this are things like   1) Half (or more) of the local data bus is not connected … most likely the read.  2) Core requires a dedicated resynch clock and one has not been wired up  3) Read request is tied low.  4) Add constraints has not been applied  --- Quote End ---     It seems not because of the "common cause", what i design is under Quartus 7.2 and used the core DDR2/DDR sdram V7.2, there is no need a dedicated resynch clock ,and all of the local data bus is completed connected,but it still report that error, i have no idea how this happend!

[Altera_Forum]

*bump* 

 I am experiencing exactly the same problem seaman. Does anyone have a solution what the problem could be??   Thanks

[Altera_Forum]

I have suffered the same trouble 

 Some un-suitbale settings of advanced parameters result this. But i don't know which setting results this and why.   Thanks to the answers above