DDR2 HP Controller Simulation

[Altera_Forum]

Hi, 

 I'm trying to simulate the DDR2 HP SDRAM controller in conjunction with a Hynix DDR2 memory model. As I'm developing in vhdl I compile the following auto generated files for the controller: ddrsdram_phy_alt_mem_phy_pll_ciii.vhd ddrsdram_auk_ddr_hp_controller_wrapper.vho ddrsdram_phy_alt_mem_phy_sequencer_wrapper.vho ddrsdram_controller_phy.vhd ddrsdram.vhd  This works perfectly in the simulation with the auto generated memory model: ddrsdram_mem_model.vhd  But if I switch to the Hynix Model (HY5PS121621F.vhd) I don't get rdata_valid signals back from the ddr controller. Despite correct dq and dqs signals from the memory model. Maybe a delta cycle problem? Or a limitation of the simulation model? I did a cosimulation with the Hynix and the Altera Model. The difference is that the Hynix Model has got a greater latency than the Altera Model on page changes.  This is what I want anyway, as I measured greater latencies in the "real" hardware. Any ideas how to get a better ddr2 model working with the Altera Controller in the simulation?  Cheers, Alex

[Altera_Forum]

Hi ddtehlert, 

 Add rigth propagation delays to CK, DQS and command pins (cas, ras, wen). Does hynyx model report any violations?

[Altera_Forum]

Is the RAS and CAS latency the same in the DDR MegaWizard, the Altera Model and the Hynix model? 

 I suspect the settings in the MegaWizard don't match the real memory device.

[Altera_Forum]

Thanks for your hints, 

 @cms: I have transport-constructs for all signals, currently I'm just delaying them for 0.1 ns.  @cajun-rat: That was a good point, as I had the CAS Latency set to 5 and 3 would have been enough. But anyway the memory did send data on a read request.  Now I changed to Quartus 8.1 and updated the memory controller and it works.  Thanks, ddtehlert