DDR2 Memory Interfaced as Avalon Slave

[Altera_Forum]

Hi, 

How is the Local side of the High speed DDR2 Controller mapped to Avalon MMslave port. I understand that DDR2 Core comes by default with an Avalon MM slave IF when created in SOPC flow!! For the DDR2 Slave it gives the entire address range that is accessible.Problem here is i have Avalon MM Master with 32-Bit wide data bus and DDR2 controller as Avalon MM Slave and has 128-Bit wide data bus. I assume that i need to generate only Write address [32-Bit], Write data,Read ,Read data and Monitor Wait request as any normal Avalon MM Master does for writing into the DDR2 SDRAM and the master arbitrer will take care to generate the Local bus timings accordingly.    ENTITY altmemddr IS PORT ( local_address : IN STD_LOGIC_VECTOR (24 DOWNTO 0); local_write_req : IN STD_LOGIC; local_read_req : IN STD_LOGIC; local_burstbegin : IN STD_LOGIC; local_wdata : IN STD_LOGIC_VECTOR (127 DOWNTO 0); local_be : IN STD_LOGIC_VECTOR (15 DOWNTO 0); local_size : IN STD_LOGIC; dqs_delay_ctrl_import : IN STD_LOGIC_VECTOR (5 DOWNT global_reset_n : IN STD_LOGIC; pll_ref_clk : IN STD_LOGIC; soft_reset_n : IN STD_LOGIC; local_ready : OUT STD_LOGIC; local_rdata : OUT STD_LOGIC_VECTOR (127 DOWNTO 0); local_rdata_valid : OUT STD_LOGIC; reset_request_n : OUT STD_LOGIC; mem_odt : OUT STD_LOGIC_VECTOR (0 DOWNTO 0); mem_cs_n : OUT STD_LOGIC_VECTOR (0 DOWNTO 0); mem_cke : OUT STD_LOGIC_VECTOR (0 DOWNTO 0); mem_addr : OUT STD_LOGIC_VECTOR (13 DOWNTO 0); mem_ba : OUT STD_LOGIC_VECTOR (2 DOWNTO 0); mem_ras_n : OUT STD_LOGIC; mem_cas_n : OUT STD_LOGIC; mem_we_n : OUT STD_LOGIC; mem_dm : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); local_refresh_ack : OUT STD_LOGIC; local_wdata_req : OUT STD_LOGIC; local_init_done : OUT STD_LOGIC; reset_phy_clk_n : OUT STD_LOGIC; dll_reference_clk : OUT STD_LOGIC; phy_clk : OUT STD_LOGIC; mem_clk : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0); mem_clk_n : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0); mem_dq : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0); mem_dqs : INOUT STD_LOGIC_VECTOR (3 DOWNTO 0) ); END altmemddr;

[Altera_Forum]

Yes. The SOPC system fabric will deal with the differences between your 32 bit master and the 128 bit slave. It accomplishes this by only applying the Byte Enables for the appropriate 32 bits as you are writing data, (and muxing the correct data as well) 

 Pete