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Hello,
I've the following design on my Cyclone III Dev. Board: - NiosII writes data to DDR2-RAM - When writing data finishes NiosII activates SGDMA to put all this data to TSE. TSE then transmitted this data... First I used OnChipMemory instead of DDR2-RAM. I reached an output-rate at TSE round about 80MBytes/sec. But now I want to use DDR2-RAM with DDR2 SDRAM High-Performance Controller because I have much more data to store. I only reached an output-rate at TSE round about 17MBytes/sec. What can I do to increase the output-rate of TSE with using DDR2-RAM? Is there any possibility? Thanks for every hint! tonibLink Copied
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