DDR2 SDRAM HPC simulation with ECC enabled

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DDR2 SDRAM HPC simulation with ECC enabled

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Hi,

I am simulating my design with DDR2 SDRAM High Performance Controller and ECC enabled. Version is 7.2. The HPC is interfaced to Avalon Bus and its ECC slave port is not used. The data width is 64-bit and burst width is 4. All the inputs of ECC port are connected to zero and outputs are left open.

I wrote 10 bursts into DDR memory model (VHDL-based) and trying to read the written bursts. After reading the 1st burst (4, 64-bit words), the local_ready pin of HPC controller core is going X. As I am simulating with VHO files, I am not able debug deep into core.

What could cause local_ready pin go X???

Any ideas for debug are most welcome and appriciated.

Thank you,

Regards,

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