DDR2 Uniphy fails Core (setup) timing

[Altera_Forum]

I'm trying to get a design working on a Stratix IV GX 230 (DE4-230) that uses dual DDR2 Uniphy controllers. Each controller is independently driving a DDR2-800 SODIMM (each x64 interface width). I had the design working with a single DDR2 controller at 200MHz full-rate (but just *barely* passing timing). Now with 2 controllers I am unable to get it to ever pass timing at 200, 150, 166, 250, or 300MHz - even though the hardware should be capable of running both interfaces at 400MHz. For the record, I am using the Qsys DDR2 controller component as this is seems the most practical way to integrate the DDR2 cores into my system (which uses a lot of other Qsys Avalon-MM and Avalon-ST stuff including many custom IP-cores). 

 I am always getting failures in reported in the "Core (setup)" section of the DDR timing report between *:altdq_dqs2_inst|read_data_out [*] and *:uread_fifo|data_stored [*] [*]. As far as I understand this is part of the read datapath where data is captured (using DQS as clock) and written into a FIFO. For reasons I don't understand (I am not a DDR2 expert and the Altera documentation is rather unhelpful here) I seem to be getting very consistent but negative slacks on these paths.  I have attached a screenshot of the timing report for one of the failing paths, they all look very similar and the delays are well matched (all of them have approx. -0.7 to -0.8ns slack, on both DDR2 controllers). Memory frequency here was set to 250MHz but I get virtually the same results at other memory clock frequencies too.  My questions about this: 1) Why is Clock Delay so high? / Should it be this high? 2) Why did the (Altera-provided / autogenerated) SDC file for the controller(s) set Max Delay to -0.050ns? Does this make any sense? 3) What might help resolve the issue?  FYI I am using Quartus 15.1.  Thanks for your time.  edit: The forum helpfully decided my screenshot was too readable so it scaled the image down and JPEG'd it. Here is an external link to the image I tried to attach: http://i.imgur.com/vvydwmz.png