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Altera_Forum
Honored Contributor I
784 Views

DDR2 calibration fail using cyclone IV device

I am using cyclone IV device connecting to a DDR2 sdram. Now I want to verify if connection between FPGA and DDR2 is OK. So i instantiated a ddr2_controller_with_altmemphy and using the example_top as top level entry. After I compile all the project there is no error or timing vilation. But after I download the sof to FPGA, ddr2 calibration fail. After I add the signal in signal_tapII, I can see that afer the seq enter Calculate Read Resynchronization Phase (s_rrp_seek), then the ctl_cal_fail asserted. Here is the signal_tap waveform. Can anyone give me some suggestion. Thanks!  

https://alteraforum.com/forum/attachment.php?attachmentid=14025&stc=1
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Altera_Forum
Honored Contributor I
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https://alteraforum.com/forum/attachment.php?attachmentid=14028&stc=1  

--- Quote Start ---  

I am using cyclone IV device connecting to a DDR2 sdram. Now I want to verify if connection between FPGA and DDR2 is OK. So i instantiated a ddr2_controller_with_altmemphy and using the example_top as top level entry. After I compile all the project there is no error or timing vilation. But after I download the sof to FPGA, ddr2 calibration fail. After I add the signal in signal_tapII, I can see that afer the seq enter Calculate Read Resynchronization Phase (s_rrp_seek), then the ctl_cal_fail asserted. Here is the signal_tap waveform. Can anyone give me some suggestion. Thanks!  

https://alteraforum.com/forum/attachment.php?attachmentid=14025&stc=1  

--- Quote End ---  

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